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gs4901b/GS4900B sd clock and ti ming generator with genlock 1 of 102 gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 www.gennum.com key features video clock synthesis ? pre-programmed for 4 video clock periods (14.32 mhz, 27 mhz, 36 mhz, and 54 mhz) ? accuracy of free-running clock frequency limited only by crystal reference ? one differential and two single-ended video clock outputs ? each clock may be individually delayed for skew control ? video output clock may be directly connected to gennum?s serializers for a smpte-compliant sdi output audio clock synthesis (gs4901b only) ? three audio clock outputs ? generates any audio clock up to 512*96khz ? pre-programmed for 7 audio clocks timing generation ? generates up to 8 timing signals at a time ? choose from 9 pre-programmed timing signals: h and v sync and blanking, f sync, f digital, afs (gs4901b only), display enable, 10fid, and up to 4 user-defined timing signals ? pre-programmed to generate timing for 9 different video formats genlock capability ? clocks may be free-running or genlocked to an input reference with a variable offset step size of 100-200ps (depending on exact clock frequency) ? variable timing offset step size of 100-200ps up to one frame ? output may be cross-locked to a different input reference ? freeze operation on loss of reference ? optional crash or drift lock on application of reference ? automatic input format detection general features ? reduces design complexity and saves board space - 9mm x 9mm package plus crystal reference replaces multiple vcxos, plls and timing generators ? pb-free and rohs compliant ? low power operation typically 300mw ? 1.8v core and 1.8v or 3.3v i/o power supplies ? 64-pin qfn package applications ? video cameras; digital audio and/or video recording/play back devices; digital audio and/or video processing devices; computer/video displays; dvd/mpeg devices; digital set top boxes; video projectors; high definition video systems; multi-media pc applications description the gs4901b is a highly flexible, digitally controlled clock synthesis circuit and timing generator with genlock capability. it can be used to generate video and audio clocks and timing signals, and allows multiple devices to be genlocked to an input reference. the GS4900B includes all the features of the gs4901b, but does not offer audio clocks or afs pulse generation. the gs4901b/GS4900B will recognize input reference signals conforming to 36 different video standards, and will genlock the output timing information to the incoming reference. the gs4901b/GS4900B supports cross-locking, allowing the output to be genlocked to an incoming reference that is different from the output video standard selected. the user may select to output one of 4 different video sample clock rates. the chosen clock frequency can be further divided using internal dividers, and is available on two video clock outputs and one lvds video clock output pair. the video clocks are frequency and phased-locked to the horizontal timing reference, and can be individually delayed with respect to the timing outputs for clock skew control. eight user-selectable timing outputs are provided that can automatically produce the following timing signals for 9 different video formats: hsync, hblanking, vsync, vblanking, f sync, f digital, afs (gs4901b only), de, and 10fid. these timing outputs may be locked to the input reference signal for genlock timing and may be phase adjusted via internal registers. in addition, the gs4901b provides three audio sample clock outputs that can produce audio clocks up to 512fs with fs ranging from 9.7khz to 96khz. audio to video phasing is accomplished by an external 10fid input reference, a 10fid signal specified via internal registers, or a user-programmed audio frame sequence. the gs4901b/GS4900B is pb-free, and the encapsulation compound does not contain halogenated flame retardant (rohs compliant).
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 2 of 102 gs4901b functional block diagram clock synthesis and control flywheel and video timing generator input reference rate identification and control crosspoint video clock divide audio clock divide 3x video clock delay adjust application programming interace hsync vsync fsync 10fid lock_lost ref_lost vid_std[5:0] asr_sel[2:0] x1 x2 timing_out_8 timing_out_7 timing_out_6 timing_out_5 timing_out_4 timing_out_3 timing_out_2 timing_out_1 pclk1 pclk2 pclk3 aclk1 aclk2 aclk3 pclk3 genlock pclk aclk_512 aclk_384 10fid de h blanking h sync user[4:1] ref_rate 27mhz clock phase adjust jtag/host sclk_tclk sdin_tdi sdout_tdo cs_tms v blanking v sync f digital f sync afs
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 3 of 102 GS4900B functional block diagram clock synthesis and control flywheel and video timing generator input reference rate identification and control crosspoint video clock divide 3x video clock delay adjust application programming interace hsync vsync fsync 10fid ref_lost vid_std[5:0] x1 x2 timing_out_8 timing_out_7 timing_out_6 timing_out_5 timing_out_4 timing_out_3 timing_out_2 timing_out_1 pclk1 pclk2 pclk3 pclk3 genlock pclk 10fid de h blanking h sync user[4:1] ref_rate 27mhz clock phase adjust jtag/host sclk_tclk sdin_tdi sdout_tdo cs_tms v blanking v sync f digital f sync lock_lost
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 4 of 102 contents key features................................................................................................................... .....................................1 applications................................................................................................................... ......................................1 description.................................................................................................................... .......................................1 1. pin out..................................................................................................................... ..........................................7 1.1 gs4901b pin assignment .................................................................................................... ...........7 1.2 GS4900B pin assignment .................................................................................................... ...........8 1.3 pin descriptions .......................................................................................................... ......................9 1.4 pre-programmed recognized video standards .................................................................. 19 1.5 output timing signals ..................................................................................................... ............ 23 2. electrical characteristics .................................................................................................. ....................... 27 2.1 absolute maximum ratings .................................................................................................. ..... 27 2.2 dc electrical characteristics ............................................................................................. ........ 27 2.3 ac electrical characteristics ............................................................................................. ........ 31 2.4 solder reflow profiles .................................................................................................... .............. 34 3. detailed description........................................................................................................ .......................... 35 3.1 functional overview ....................................................................................................... ............. 35 3.2 modes of operation ........................................................................................................ .............. 35 3.2.1 genlock mode............................................................................................................. ........ 35 3.2.2 free run mode ............................................................................................................ ....... 39 3.3 output timing format selection ............................................................................................ .. 40 3.4 input reference signals ................................................................................................... ............ 41 3.4.1 hsync, vsync, and fsync.......................................................................................... 41 3.4.2 10fid .................................................................................................................... ................. 42 3.4.3 automatic polarity recognition ................................................................................... 42 3.5 reference format detector ................................................................................................. ....... 43 3.5.1 horizontal and vertical timing characteristic measurements ......................... 43 3.5.2 input reference validity................................................................................................. 44 3.5.3 behaviour on loss and re-acquisition of the reference signal......................... 45 3.5.4 allowable frequency drift on the reference .......................................................... 47 3.6 genlock ................................................................................................................... .......................... 47 3.6.1 adjustable locking time................................................................................................. 4 9 3.6.2 adjustable loop bandwidth .......................................................................................... 49 3.6.3 locking to digital timing from a deserializer ......................................................... 52 3.7 clock synthesis ........................................................................................................... ................... 52 3.7.1 video clock synthesis.................................................................................................... .. 52 3.7.2 audio clock synthesis (gs4901b only) ...................................................................... 54 3.8 video timing generator .................................................................................................... .......... 58 3.8.1 10 field id pulse........................................................................................................ ......... 58 3.8.2 audio frame synchronizing pulse (g s4901b only)... ............................................ 59 3.8.3 user_1~4................................................................................................................. ............ 60 3.8.4 timing_out pins .......................................................................................................... ... 62 3.9 extended audio mode for hd demux using the gennum audio core ...................... 63
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 5 of 102 3.10 gspi host interface ...................................................................................................... ............... 64 3.10.1 command word description ...................................................................................... 66 3.10.2 data read and write timing ....................................................................................... 66 3.10.3 configuration and status registers........................................................................... 67 3.11 jtag ..................................................................................................................... ............................ 93 3.12 device power-up .......................................................................................................... .............. 94 3.12.1 power supply sequencing ........................................................................................... 94 3.13 device reset ............................................................................................................. ..................... 94 4. application reference design ................................................................................................ ............... 95 4.1 gs4901b typical application circuit ..................................................................................... 95 4.2 GS4900B typical application circuit ..................................................................................... 96 5. references & relevant standards ............................................................................................. ............ 97 6. package & ordering information .............................................................................................. ............ 98 6.1 package dimensions ........................................................................................................ ............. 98 6.2 recommended pcb footprint ................................................................................................. .. 99 6.3 packaging data ............................................................................................................ ................... 99 6.4 ordering information ...................................................................................................... ........... 100 7. revision history............................................................................................................ ............................ 101 list of figures gs4901b functional block diagram .............................................................................................. ........... 2 GS4900B functional block diagram .............................................................................................. ........... 3 figure 1-1: xtal1 and xtal2 reference circuits .............................................................................. 18 figure 2-1: pclk to timing_out signal output timing ................................................................. 32 figure 2-2: maximum pb-free solder reflow profile (preferred) .................................................. 34 figure 2-3: standard pb solder reflow profile ................................................................................ .... 34 figure 3-1: sd-hd calculation ................................................................................................. ................. 38 figure 3-2: output accuracy and modes of operation ..................................................................... 40 figure 3-3: example hsync, vsync, and fsync analog input timing from a sync separator ................................................................................................................ ................................ 41 figure 3-4: example h blanking, v blanking, and f digital input timing from an sdi deserializer .............................................................................................................. ................................ 41 figure 3-5: 10fid input timing ................................................................................................ ................. 42 figure 3-6: default 10fid output timing ....................................................................................... ....... 58 figure 3-7: optional 10fid output timing ...................................................................................... ..... 59 figure 3-8: afs output timing ................................................................................................. ................ 60 figure 3-9: user programmable output signal .................................................................................. 6 1 figure 3-10: audio clock block diagram for hd demux operation ........................................... 64 figure 3-11: gspi application interface connection ........................................................................ 65 figure 3-12: command word format .............................................................................................. ....... 66 figure 3-13: data word format ................................................................................................. ............... 66 figure 3-14: gspi read mode timing ............................................................................................ ......... 67 figure 3-15: gspi write mode timing ........................................................................................... ......... 67 figure 3-16: in-circuit jtag .................................................................................................. .................... 93 figure 3-17: system jtag ...................................................................................................... ..................... 94
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 6 of 102 list of tables table 1-1: pin descriptions .................................................................................................... ........................ 9 table 1-2: recognized video standards.......................................................................................... ....... 20 table 1-3: output timing signals ............................................................................................... .............. 23 table 2-1: dc electrical characteristics ....................................................................................... .......... 27 table 2-2: ac electrical characteristics ....................................................................................... .......... 31 table 2-3: suggested external crystal specification ......................................................................... 33 table 3-1: clock_phase_offset [15:0] encoding scheme.................................................................. 37 table 3-2: ambiguous standard identification................................................................................... . 45 table 3-3: max_ref_delta encoding scheme....................................................................................... 47 table 3-4: cross-reference genlock table....................................................................................... ...... 48 table 3-5: integer constant value.............................................................................................. .............. 51 table 3-6: video clock phase adjustment host settings.................................................................. 54 table 3-7: audio sample rate select............................................................................................ ........... 55 table 3-8: audio clock divider ................................................................................................. ................ 55 table 3-9: encoding scheme for afs_reset_window ...................................................................... 56 table 3-10: audio sampling frequency to video frame rate synchronization...................... 57 table 3-11: crosspoint select.................................................................................................. ................... 62 table 3-12: gspi timing parameters ............................................................................................. .......... 66 table 3-13: configuration and status registers................................................................................. .. 68 table 5-1: references & relevant standards ..................................................................................... ... 97
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 7 of 102 1. pin out 1.1 gs4901b pin assignment lock_lost genlock 1 ref_lost vid_pll_vdd vid_pll_gnd xtal_vdd x1 x2 xtal_gnd core_gnd analog_vdd nc analog_gnd aud_pll_gnd aud_pll_vdd 10fid hsync io_vdd sdout_tdo sdin_tdi sclk_tclk phs_gnd phs_vdd pclk1&2_vdd pclk1&2_gnd pclk1 io_vdd pclk2 lvds/pclk3_gnd pclk3 lvds/pclk3_vdd core_vdd timing_out_8 timing_out_7 timing_out_6 timing_out_5 timing_out_4 timing_out_3 timing_out_2 timing_out_1 io_vdd asr_sel0 asr_sel1 asr_sel2 io_vdd aclk3 aclk2 aclk1 vid_std5 core_vdd vid_std0 vid_std4 vid_std3 vid_std2 vid_std1 nc fsync io_vdd vsync reset cs_tms pclk3 16 17 32 33 48 49 64 2 3 4 5 6 7 8 9 10 11 12 13 14 15 18 19 20 21 23 24 25 26 27 28 29 30 31 22 34 35 36 37 38 39 40 41 42 43 44 45 46 47 50 51 52 53 54 55 56 57 58 59 60 61 62 63 nc ground pad (bottom of package) jtag/host gs4901b 64-pin qfn (top view)
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 8 of 102 1.2 GS4900B pin assignment lock_lost genlock GS4900B 64-pin qfn (top view) 1 ref_lost vid_pll_vdd vid_pll_gnd xtal_vdd x1 x2 xtal_gnd core_gnd analog_vdd nc analog_gnd 10fid hsync io_vdd sdout_tdo sdin_tdi sclk_tclk phs_gnd phs_vdd pclk1&2_vdd pclk1&2_gnd pclk1 io_vdd pclk2 lvds/pclk3_gnd pclk3 lvds/pclk3_vdd core_vdd timing_out_8 timing_out_7 timing_out_6 timing_out_5 timing_out_4 timing_out_3 timing_out_2 timing_out_1 io_vdd io_vdd nc nc nc vid_std5 core_vdd vid_std0 vid_std4 vid_std3 vid_std2 vid_std1 nc fsync io_vdd vsync reset cs_tms pclk3 16 17 32 33 48 49 64 2 3 4 5 6 7 8 9 10 11 12 13 14 15 18 19 20 21 23 24 25 26 27 28 29 30 31 22 34 35 36 37 38 39 40 41 42 43 44 45 46 47 50 51 52 53 54 55 56 57 58 59 60 61 62 63 nc ground pad (bottom of package) jtag/host analog_gnd analog_gnd analog_gnd analog_gnd analog_gnd
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 9 of 102 1.3 pin descriptions table 1-1: pin descriptions pin number name timing typ e description 1lo c k_lo s tnon s yn c hronous output s tatu s s i g nal output s i g nal levels are lv c mo s /lvttl c ompati b le. this pin will b e hi g h if the output is not g enlo c ke d to the input. the gs 4901b/ gs 4900b monitors the output pixel/line c ounters, as well as the internal lo c k status from the g enlo c k b lo c k an d asserts lo c k_lo s t hi g h if it is d etermine d that the output is not g enlo c ke d to the input. this pin will b e low if the d evi c e su cc essfully g enlo c ks the output c lo c k an d timin g si g nals to the input referen c e. if lo c k_lo s t is low, the referen c e timin g g enerator outputs will b e phase lo c ke d to the d ete c te d referen c e si g nal, pro d u c in g an output in a cc or d an c e with the vi d eo stan d ar d sele c te d b y the vid_ s td[5:0] pins. 2 ref_lo s tnon s yn c hronous output s tatu s s i g nal output s i g nal levels are lv c mo s /lvttl c ompati b le. this pin will b e hi g h if: ? no input referen c e si g nal is applie d to the d evi c e; or ? the input referen c e applie d d oes not meet the minimum/maximum timin g requirements d es c ri b e d in s e c tion 3.5.2 on pa g e 44 . this pin will b e low otherwise. if the referen c e si g nal is remove d when the d evi c e is in g enlo c k mo d e, ref_lo s t will g o hi g h an d the gs 4901b/ gs 4900b will enter freeze mo d e (see s e c tion 3.2.1.2 on pa g e 39 ). 3 vid_pll_vdd ? power s upply most positive power supply c onne c tion for the vi d eo c lo c k synthesis internal b lo c k. c onne c t to +1.8v d c . 4 vid_pll_ g nd ? power s upply g roun d c onne c tion for the vi d eo c lo c k synthesis internal b lo c k. c onne c t to g nd. 5 xtal_vdd ? power s upply most positive power supply c onne c tion for the c rystal b uffer. c onne c t to either +1.8v d c or +3.3v d c . note: c onne c t to +3.3v for minimum output p c lk jitter. 6 x1 non s yn c hronous input analo g s i g nal input c onne c t to a 27mhz c rystal or a 27mhz external c lo c k sour c e. s ee fi g ure 1-1 . 7x2 non s yn c hronous output analo g s i g nal output c onne c t to a 27mhz c rystal, or leave this pin open c ir c uit if an external c lo c k sour c e is applie d to pin 6 . s ee fi g ure 1-1 . 8xtal_ g nd ? power s upply g roun d c onne c tion for the c rystal b uffer. c onne c t to g nd.
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 10 of 102 9 c ore_ g nd ? power s upply g roun d c onne c tion for c ore an d i/o. s ol d er to the g roun d plane of the appli c ation b oar d . note: the c ore_ g nd pin shoul d b e sol d ere d to the same main g roun d plane as the expose d g roun d pa d on the b ottom of the d evi c e. 10 analo g _vdd ? power s upply most positive power supply c onne c tion for the analo g input b lo c k. c onne c t to +1.8v d c . 11, 20, 6 3n c ? ? do not c onne c t. 12 analo g _ g nd ? power s upply g roun d c onne c tion for the analo g input b lo c k. c onne c t to g nd. 13 aud_pll_ g nd ( gs 4901b only) ?power s upply g roun d c onne c tion for the au d io c lo c k synthesis internal b lo c k. c onne c t to g nd. analo g _ g nd ( gs 4900b only) ?power s upply g roun d c onne c tion for the analo g input b lo c k. c onne c t to g nd. 14 aud_pll_vdd ( gs 4901b only) ?power s upply most positive power supply c onne c tion for the au d io c lo c k synthesis internal b lo c k. c onne c t to +1.8v d c . analo g _ g nd ( gs 4900b only) ?power s upply g roun d c onne c tion for the analo g input b lo c k. c onne c t to g nd. 15 10fid non s yn c hronous input referen c e s i g nal input s i g nal levels are lv c mo s /lvttl c ompati b le. the 10fid external referen c e si g nal is applie d to this pin b y the appli c ation layer. 10fid d efines the fiel d in whi c h the vi d eo an d au d io c lo c k phase relationship is d efine d a cc or d in g to s mpte 318-m. it is also use d to d efine a 3:2 vi d eo c a d en c e. note: if the input referen c e format d oes not in c lu d e a 10 fiel d id si g nal, this pin shoul d b e hel d low. s ee s e c tion 3.4.2 on pa g e 42 . 1 6 h s yn c non s yn c hronous input referen c e s i g nal input s i g nal levels are lv c mo s /lvttl c ompati b le. the h s yn c external referen c e si g nal is applie d to this pin b y the appli c ation layer. when the gs 4901b/ gs 4900b is operatin g in g enlo c k mo d e, the d evi c e senses the polarity of the h s yn c input automati c ally, an d referen c es to the lea d in g e dg e. this si g nal must a d here to one of the 3 6 d efine d vi d eo stan d ar d s supporte d b y the d evi c e. in this mo d e of operation, the h s yn c input provi d es a horizontal s c annin g referen c e si g nal. the h s yn c si g nal may have analo g timin g , su c h as from a syn c separator, or may b e d i g ital su c h as from an s di d eserializer. s e c tion 1.4 on pa g e 19 d es c ri b es the 3 6 vi d eo formats re c o g nize d b y the gs 4901b/ gs 4900b. table 1-1: pin descriptions (continued) pin number name timing typ e description
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 11 of 102 17 v s yn c non s yn c hronous input referen c e s i g nal input s i g nal levels are lv c mo s /lvttl c ompati b le. the v s yn c external referen c e si g nal is applie d to this pin b y the appli c ation layer. when the gs 4901b/ gs 4900b is operatin g in g enlo c k mo d e, the d evi c e senses the polarity of the v s yn c input automati c ally, an d referen c es to the lea d in g e dg e. this si g nal must a d here to one of the 3 6 d efine d vi d eo stan d ar d s supporte d b y the d evi c e. in this mo d e of operation, the v s yn c input provi d es a verti c al s c annin g referen c e si g nal. the v s yn c si g nal may have analo g timin g , su c h as from a syn c separator, or may b e d i g ital su c h as from an s di d eserializer. s e c tion 1.4 on pa g e 19 d es c ri b es the 3 6 vi d eo formats re c o g nize d b y the gs 4901b/ gs 4900b. 18, 31, 38, 50, 6 2 io_vdd ? power s upply most positive power supply c onne c tion for the d i g ital i/o si g nals. c onne c t to either +1.8v d c or +3.3v d c . note: all five io_vdd pins must b e powere d b y the same volta g e. 19 f s yn c non s yn c hronous input referen c e s i g nal input s i g nal levels are lv c mo s /lvttl c ompati b le. the f s yn c external referen c e si g nal is applie d to this pin b y the appli c ation layer. the first fiel d is d efine d as the fiel d in whi c h the first b roa d pulse (also known as serration) is in the first half of a line. the f s yn c si g nal shoul d b e set hi g h d urin g the first fiel d for syn c - b ase d referen c es. then this si g nal must a d here to one of the 3 6 d efine d vi d eo stan d ar d s supporte d b y the d evi c e. in this mo d e of operation, the f s yn c input provi d es an o dd /even fiel d input referen c e. the f s yn c si g nal may have analo g timin g , su c h as from a syn c separator, or may b e d i g ital su c h as from an s di d eserializer. s e c tion 1.4 on pa g e 19 d es c ri b es the 3 6 vi d eo formats re c o g nize d b y the gs 4901b/ gs 4900b. for b lankin g - b ase d referen c es, the f s yn c si g nal shoul d b e set hi g h d urin g the se c on d fiel d . note: if the input referen c e format d oes not in c lu d e an f syn c si g nal, this pin shoul d b e hel d low. 27, 25, 24, 23, 22, 21 vid_ s td[5:0] non s yn c hronous input c ontrol s i g nal input s s i g nal levels are lv c mo s /lvttl c ompati b le. vi d eo s tan d ar d s ele c t. use d to sele c t the d esire d vi d eo format for vi d eo c lo c k an d timin g si g nal g eneration. 4 d ifferent vi d eo sample c lo c ks, as well as 9 d ifferent vi d eo format timin g si g nal outputs may b e sele c te d usin g these pins. note: the vid_ s td[5:4] pins shoul d b e g roun d e d b y the appli c ation layer sin c e these pins are not require d to sele c t output vi d eo stan d ar d s 1 to 10. for d etails on the supporte d vi d eo stan d ar d s an d vi d eo c lo c k frequen c y sele c tion, please see s e c tion 1.4 on pa g e 19 . 2 6 , 44 c ore_vdd ? power s upply most positive power supply c onne c tion for the d i g ital c ore. c onne c t to +1.8v d c . table 1-1: pin descriptions (continued) pin number name timing typ e description
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 12 of 102 28, 29, 30 a c lk1 a c lk2 a c lk3 ( gs 4901b only) ? output c lo c k s i g nal output s s i g nal levels are lv c mo s /lvttl c ompati b le. au d io output c lo c k si g nals. a c lk1, a c lk2, an d a c lk3 present au d io sample rate c lo c k outputs to the appli c ation layer. by d efault, after system reset, the au d io c lo c k output pins of the d evi c e provi d e c lo c k si g nals as follows: a c lk1 = 25 6 fs a c lk2 = 6 4fs a c lk3 = fs, where fs is the fun d amental samplin g frequen c y. the fun d amental samplin g frequen c y is sele c te d usin g a s r_ s el[2:0]. a dd itional samplin g frequen c ies may b e pro g ramme d in the host interfa c e. it is also possi b le to sele c t d ifferent d ivision ratios for ea c h of the au d io c lo c k outputs b y pro g rammin g d esi g nate d re g isters in the host interfa c e. c lo c k outputs of 512fs, 384fs, 25 6 fs, 192fs, 128fs, 6 4fs, fs an d z b it are sele c ta b le on a pin- b y-pin b asis. note: a c lk1-3 will have a 50% d uty c y c le, unless fs is sele c te d as 9 6 khz an d the host interfa c e is c onfi g ure d su c h that one of the three a c lk pins is set to output a c lo c k si g nal at 192fs or 384fs. if this is the c ase, then a 512fs c lo c k will have a 33% d uty c y c le. these si g nals will b e hi g h impe d an c e when a s r_ s el[2:0] = 000 b . n c ( gs 4900b only) ? ? do not c onne c t. 32, 33, 34 a s r_ s el[2:0] ( gs 4901b only) non s yn c hronous input c ontrol s i g nal input s s i g nal levels are lv c mo s /lvttl c ompati b le. au d io s ample rate s ele c t. use d to sele c t the fun d amental samplin g frequen c y, fs, of the au d io c lo c k outputs. s ee ta b le 3-7 . when a s r_ s el[2:0] = 000 b , au d io c lo c k g eneration will b e d isa b le d an d the a c lk1 to a c lk3 pins will b e hi g h impe d an c e. in this c ase, aud_pll_vdd (pin 14) may b e c onne c te d to g nd to minimize noise an d power c onsumption. analo g _ g nd ( gs 4900b only) ?power s upply g roun d c onne c tion for the analo g input b lo c k. c onne c t to g nd. 35 timin g _out_1 s yn c hronous with p c lk1 ~ p c lk3 output timin g s i g nal output s i g nal levels are lv c mo s /lvttl c ompati b le. s ele c ta b le timin g output. s ele c ta b le from: h syn c ; h b lankin g ; v syn c ; v b lankin g ; f syn c ; f d i g ital; display ena b le; 10 fiel d id (film c a d en c e); af s vi d eo/au d io timin g ( gs 4901b only); u s er_1~4. s ee s e c tion 1.5 on pa g e 23 for si g nal d es c riptions. note: default output is h s yn c . the c urrent d rive c apa b ility of this pin may b e set hi g h or low via d esi g nate d re g isters in the host interfa c e. by d efault, the c urrent d rive will b e low. this si g nal will b e hi g h impe d an c e when vid_ s td[5:0] = 00h. table 1-1: pin descriptions (continued) pin number name timing typ e description
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 13 of 102 3 6 timin g _out_2 s yn c hronous with p c lk1 ~ p c lk3 output timin g s i g nal output s i g nal levels are lv c mo s /lvttl c ompati b le. s ele c ta b le timin g output. s ele c ta b le from: h syn c ; h b lankin g ; v syn c ; v b lankin g ; f syn c ; f d i g ital; display ena b le; 10 fiel d id (film c a d en c e); af s vi d eo/au d io timin g ( gs 4901b only); u s er_1~4. s ee s e c tion 1.5 on pa g e 23 for si g nal d es c riptions. note: default output is h b lankin g . the c urrent d rive c apa b ility of this pin may b e set hi g h or low via d esi g nate d re g isters in the host interfa c e. by d efault, the c urrent d rive will b e low. this si g nal will b e hi g h impe d an c e when vid_ s td[5:0] = 00h. 37 timin g _out_3 s yn c hronous with p c lk1 ~ p c lk3 output timin g s i g nal output s i g nal levels are lv c mo s /lvttl c ompati b le. s ele c ta b le timin g output. s ele c ta b le from: h syn c ; h b lankin g ; v syn c ; v b lankin g ; f syn c ; f d i g ital; display ena b le; 10 fiel d id (film c a d en c e); af s vi d eo/au d io timin g ( gs 4901b only); u s er_1~4. s ee s e c tion 1.5 on pa g e 23 for si g nal d es c riptions. note: default output is v s yn c . the c urrent d rive c apa b ility of this pin may b e set hi g h or low via d esi g nate d re g isters in the host interfa c e. by d efault, the c urrent d rive will b e low. this si g nal will b e hi g h impe d an c e when vid_ s td[5:0] = 00h. 39 timin g _out_4 s yn c hronous with p c lk1 ~ p c lk3 output timin g s i g nal output s i g nal levels are lv c mo s /lvttl c ompati b le. s ele c ta b le timin g output. s ele c ta b le from: h syn c ; h b lankin g ; v syn c ; v b lankin g ; f syn c ; f d i g ital; display ena b le; 10 fiel d id (film c a d en c e); af s vi d eo/au d io timin g ( gs 4901b only); u s er_1~4. s ee s e c tion 1.5 on pa g e 23 for si g nal d es c riptions. note: default output is v b lankin g . the c urrent d rive c apa b ility of this pin may b e set hi g h or low via d esi g nate d re g isters in the host interfa c e. by d efault, the c urrent d rive will b e low. this si g nal will b e hi g h impe d an c e when vid_ s td[5:0] = 00h. table 1-1: pin descriptions (continued) pin number name timing typ e description
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 14 of 102 40 timin g _out_5 s yn c hronous with p c lk1 ~ p c lk3 output timin g s i g nal output s i g nal levels are lv c mo s /lvttl c ompati b le. s ele c ta b le timin g output. s ele c ta b le from: h syn c ; h b lankin g ; v syn c ; v b lankin g ; f syn c ; f d i g ital; display ena b le; 10 fiel d id (film c a d en c e); af s vi d eo/au d io timin g ( gs 4901b only); u s er_1~4. s ee s e c tion 1.5 on pa g e 23 for si g nal d es c riptions. note: default output is f s yn c . the c urrent d rive c apa b ility of this pin may b e set hi g h or low via d esi g nate d re g isters in the host interfa c e. by d efault, the c urrent d rive will b e low. this si g nal will b e hi g h impe d an c e when vid_ s td[5:0] = 00h. 41 timin g _out_ 6s yn c hronous with p c lk1 ~ p c lk3 output timin g s i g nal output s i g nal levels are lv c mo s /lvttl c ompati b le. s ele c ta b le timin g output. s ele c ta b le from: h syn c ; h b lankin g ; v syn c ; v b lankin g ; f syn c ; f d i g ital; display ena b le; 10 fiel d id (film c a d en c e); af s vi d eo/au d io timin g ( gs 4901b only); u s er_1~4. s ee s e c tion 1.5 on pa g e 23 for si g nal d es c riptions. note: default output is f d i g ital. the c urrent d rive c apa b ility of this pin may b e set hi g h or low via d esi g nate d re g isters in the host interfa c e. by d efault, the c urrent d rive will b e low. this si g nal will b e hi g h impe d an c e when vid_ s td[5:0] = 00h. 42 timin g _out_7 s yn c hronous with p c lk1 ~ p c lk3 output timin g s i g nal output s i g nal levels are lv c mo s /lvttl c ompati b le. s ele c ta b le timin g output. s ele c ta b le from: h syn c ; h b lankin g ; v syn c ; v b lankin g ; f syn c ; f d i g ital; display ena b le; 10 fiel d id (film c a d en c e); af s vi d eo/au d io timin g ( gs 4901b only); u s er_1~4. s ee s e c tion 1.5 on pa g e 23 for si g nal d es c riptions. note: default output is 10 fiel d id (10fid). the c urrent d rive c apa b ility of this pin may b e set hi g h or low via d esi g nate d re g isters in the host interfa c e. by d efault, the c urrent d rive will b e low. this si g nal will b e hi g h impe d an c e when vid_ s td[5:0] = 00h. table 1-1: pin descriptions (continued) pin number name timing typ e description
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 15 of 102 43 timin g _out_8 s yn c hronous with p c lk1 ~ p c lk3 output timin g s i g nal output s i g nal levels are lv c mo s /lvttl c ompati b le. s ele c ta b le timin g output. s ele c ta b le from: h syn c ; h b lankin g ; v syn c ; v b lankin g ; f syn c ; f d i g ital; display ena b le; 10 fiel d id (film c a d en c e); af s vi d eo/au d io timin g ( gs 4901b only); u s er_1~4. s ee s e c tion 1.5 on pa g e 23 for si g nal d es c riptions. note: default output is display ena b le (de). the c urrent d rive c apa b ility of this pin may b e set hi g h or low via d esi g nate d re g isters in the host interfa c e. by d efault, the c urrent d rive will b e low. this si g nal will b e hi g h impe d an c e when vid_ s td[5:0] = 00h. 45 lvd s /p c lk3_vdd ? power s upply most positive power supply c onne c tion for p c lk3 output c ir c uitry an d lvd s d river. c onne c t to +1.8v d c . 4 6 , 47 p c lk3 , p c lk3 ? output c lo c k s i g nal output s s i g nal levels are lvd s c ompati b le. differential vi d eo c lo c k output si g nal. p c lk3 / p c lk3 present a d ifferential vi d eo sample rate c lo c k output to the appli c ation layer. by d efault, after system reset, this output will operate at the fun d amental frequen c y d etermine d b y the settin g of the vid_ s td[5:0] pins. it is possi b le to d efine other non-stan d ar d fun d amental c lo c k rates usin g the host interfa c e. it is also possi b le to sele c t d ifferent d ivision ratios for the p c lk3 / p c lk3 outputs b y pro g rammin g d esi g nate d re g isters in the host interfa c e. a c lo c k output of the fun d amental rate, fun d amental rate 2, or fun d amental rate 4 may b e sele c te d . the p c lk3 / p c lk3 outputs will b e hi g h impe d an c e when vid_ s td[5:0] = 00h. 48 lvd s /p c lk3_ g nd ? power s upply g roun d c onne c tion for p c lk3 output c ir c uitry an d lvd s d river. c onne c t to g nd. 49 p c lk2 ? output c lo c k s i g nal output s i g nal levels are lv c mo s /lvttl c ompati b le. vi d eo c lo c k output si g nal. p c lk2 presents a vi d eo sample rate c lo c k output to the appli c ation layer. by d efault, after system reset, the p c lk2 output pin will operate at the fun d amental frequen c y d etermine d b y the settin g of the vid_ s td[5:0] pins. it is possi b le to d efine other non-stan d ar d fun d amental c lo c k rates usin g the host interfa c e. it is also possi b le to sele c t d ifferent d ivision ratios for the p c lk2 output b y pro g rammin g d esi g nate d re g isters in the host interfa c e. a c lo c k output of the fun d amental rate, fun d amental rate 2, or fun d amental rate 4 may b e sele c te d . by settin g d esi g nate d re g isters in the host interfa c e, the c urrent d rive c apa b ility of this pin may b e set hi g h or low. by d efault, the c urrent d rive will b e low. the p c lk2 output will b e hel d low when vid_ s td[5:0] = 00h. table 1-1: pin descriptions (continued) pin number name timing typ e description
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 16 of 102 51 p c lk1 ? output c lo c k s i g nal output s i g nal levels are lv c mo s /lvttl c ompati b le. vi d eo c lo c k output si g nal. p c lk1 presents a vi d eo sample rate c lo c k output to the appli c ation layer. by d efault, after system reset, the p c lk1 output pin will operate at the fun d amental frequen c y d etermine d b y the settin g of the vid_ s td[5:0] pins. it is possi b le to d efine other non-stan d ar d fun d amental c lo c k rates usin g the host interfa c e. it is also possi b le to sele c t d ifferent d ivision ratios for the p c lk1 output b y pro g rammin g d esi g nate d re g isters in the host interfa c e. a c lo c k output of the fun d amental rate, fun d amental rate 2, or fun d amental rate 4 may b e sele c te d . by settin g d esi g nate d re g isters in the host interfa c e, the c urrent d rive c apa b ility of this pin may b e set hi g h or low. by d efault, the c urrent d rive will b e low. the p c lk1 output will b e hel d low when vid_ s td[5:0] = 00h. 52 p c lk1&2_ g nd ? power s upply g roun d c onne c tion for p c lk1&2 c ir c uitry. c onne c t to g nd. 53 p c lk1&2_vdd ? power s upply most positive power supply c onne c tion for p c lk1&2 c ir c uitry. c onne c t to +1.8v d c . 54 ph s _vdd ? power s upply most positive power supply c onne c tion for the vi d eo c lo c k phase shift internal b lo c k. c onne c t to +1.8v d c . 55 ph s _ g nd ? power s upply g roun d c onne c tion for the vi d eo c lo c k phase shift internal b lo c k. c onne c t to g nd. 5 6j ta g /ho s t non s yn c hronous input c ontrol s i g nal input s i g nal levels are lv c mo s /lvttl c ompati b le. use d to sele c t j ta g test mo d e or host interfa c e mo d e. when set hi g h, cs _tm s , sc lk_t c lk, s dout_tdo, an d s din_tdi are c onfi g ure d for j ta g b oun d ary s c an testin g . when set low, cs _tm s , sc lk_t c lk, s dout_tdo, an d s din_tdi are c onfi g ure d as gs pi pins for normal host interfa c e operation. 57 sc lk_t c lk non s yn c hronous input s i g nal input s i g nal levels are lv c mo s /lvttl c ompati b le. s erial data c lo c k / test c lo c k. all j ta g / host interfa c e a dd ress an d d ata are shifte d into/out of the d evi c e syn c hronously with this c lo c k. host mo d e ( j ta g /ho s t = low): sc lk_t c lk operates as the host interfa c e serial d ata c lo c k, sc lk. j ta g test mo d e ( j ta g /ho s t = hi g h): sc lk_t c lk operates as the j ta g test c lo c k, t c lk. table 1-1: pin descriptions (continued) pin number name timing typ e description
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 17 of 102 58 s din_tdi s yn c hronous with sc lk_t c lk input s i g nal input s i g nal levels are lv c mo s /lvttl c ompati b le. s erial data input / test data input. host mo d e ( j ta g /ho s t = low): s din_tdi operates as the host interfa c e serial input, s din, use d to write a dd ress an d c onfi g uration information to the internal re g isters of the d evi c e. j ta g test mo d e ( j ta g /ho s t = hi g h): s din_tdi operates as the j ta g test d ata input, tdi. 59 s dout_tdo s yn c hronous with sc lk_t c lk output s i g nal input s i g nal levels are lv c mo s /lvttl c ompati b le. s erial data output / test data output. host mo d e ( j ta g /ho s t = low): s dout_tdo operates as the host interfa c e serial output, s dout, use d to rea d status an d c onfi g uration information from the internal re g isters of the d evi c e. j ta g test mo d e ( j ta g /ho s t = hi g h): s dout_tdo operates as the j ta g test d ata output, tdo. 6 0 cs _tm ss yn c hronous with sc lk_t c lk input s i g nal input s i g nal levels are lv c mo s /lvttl c ompati b le. c hip s ele c t / test mo d e s ele c t. host mo d e ( j ta g /ho s t = low): cs _tm s operates as the host interfa c e c hip sele c t, cs , an d is a c tive low. j ta g test mo d e ( j ta g /ho s t = hi g h): cs _tm s operates as the j ta g test mo d e sele c t, tm s , an d is a c tive hi g h. 6 1re s et non s yn c hronous input c ontrol s i g nal input s i g nal levels are lv c mo s /lvttl c ompati b le. use d to reset the internal operatin g c on d itions to their d efault settin g s or to reset the j ta g test sequen c e. host mo d e ( j ta g /ho s t = low): when asserte d low, all host re g isters an d fun c tional b lo c ks will b e set to their d efault c on d itions. all input an d output si g nals will b e c ome hi g h impe d an c e, ex c ept p c lk1 an d p c lk2, whi c h will b e set low. when set hi g h, normal operation of the d evi c e will resume. the user must hol d this pin low d urin g power-up an d for a minimum of 500 u s after the last supply has rea c he d its operatin g volta g e. j ta g test mo d e ( j ta g /ho s t = hi g h): when asserte d low, all host re g isters an d fun c tional b lo c ks will b e set to their d efault c on d itions an d the j ta g test sequen c e will b e hel d in reset. when set hi g h, normal operation of the j ta g test sequen c e will resume. table 1-1: pin descriptions (continued) pin number name timing typ e description
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 18 of 102 fi g ure 1-1: xtal1 an d xtal2 referen c e c ir c uits 6 4 g enlo c k non s yn c hronous input c ontrol s i g nal input s i g nal levels are lv c mo s /lvttl c ompati b le. s ele c ts g enlo c k mo d e or free run mo d e. when this pin is set low an d the d evi c e has su cc essfully g enlo c ke d the output to the input referen c e, the d evi c e will enter g enlo c k mo d e. the vi d eo c lo c k an d timin g outputs will b e frequen c y an d phase lo c ke d to the d ete c te d referen c e si g nal. when this pin is set hi g h, the vi d eo c lo c k an d the referen c e-timin g g enerator will free-run. by d efault, the gs 4901b?s au d io c lo c ks will b e g enlo c ke d to the output vi d eo c lo c k re g ar d less of the settin g of this pin. note: the user must apply a referen c e to the input of the d evi c e prior to settin g g enlo c k = low. if the g enlo c k pin is set low an d no referen c e si g nal is present, the g enerate d c lo c k an d timin g outputs of the d evi c e may c orrespon d to the internal d efault settin g s of the c hip until a referen c e is applie d . ? g roun d pa d ?? g roun d pa d on b ottom of pa c ka g e must b e sol d ere d to main g roun d plane of p c b. table 1-1: pin descriptions (continued) pin number name timing typ e description x1 38pf x2 24pf 1m 6 7 x1 x2 6 7 nc external clock external crystal connection external clock source connection notes: 1. capacitor values listed represent the total capacitance, including discrete capacitance and parasitic board capacitance. 2. x1 serves as an input, which may alternatively accept a 27mhz clock source. to accomodate this, mismatched capacitor values are recommended.
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 19 of 102 1.4 pre-programmed recognized video standards table 1-2 describes the video standards recognized by the gs4901b/GS4900B. the device will automatically recognize vid_std[5:0] = 1 to 10. in order to enable the device to recognize and lock to any of the hd reference formats defined by vid_std[5:0] = 11 to 38, the user must set the corresponding bit low in the reference_standard_disable register, located at address 11h-13h of the host interface. in addition, the user must set the hd_reference_enable bit of register 82h[7] high. please see the descriptions of the reference_standard_disable and hd_reference_enable registers in section 3.10.3 on page 67 . if an hd reference format is left disabled in the reference_standard_disable register, or if the hd_reference_enable bit is not set high in register 82h, the device will not recognize this format should it be applied to the input of the device. the user may select vid_std[5:0] = 1 or 3-10 only as output formats. if desired, the external vid_std[5:0] pins may be ignored by setting bit 1 of the video_control register, and the video standard may instead be selected via the vid_std[5:0] register of the host interface (see section 3.10.3 on page 67 ). although the external vid_std[5:0] pins will be ignored in this case, they should not be left floating. note: vid_std[5:4] should always be set low by the application layer since these pins are not required to select output video standards 1 to 10.
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 20 of 102 table 1-2: recognized video standards vid_std [5:0] system nomenclature video pclk frequency (mhz) pclks / to t a l line to t a l l i n e s / frame pclks / active line h sync width (clocks) h sync polarity v sync width (lines) v sync polarity active lines / frame scan format standard 0p c lk1&2 =low. p c lk3/p c lk3 = hi g h impe d an c e ? ? ? ??????? 14fs c 525 / 2:1 interla c e 14.32 910 525 7 6 8 6 7ne g ative 3 ne g ative 48 6s mpte 244m 2* c omposite pal 6 25 / 2:1 interla c e / 25 ?? 6 25 ? ? ne g ative 2.5 ne g ative 57 6 ? 3 6 01 525 / 2:1 interla c e 27 171 6 525 1440 127 ne g ative 3 ne g ative 48 6s mpte 125m/2 6 7m 4? 6 01 6 25 / 2:1 interla c e 27 1728 6 25 1440 127 ne g ative 2.5 ne g ative 57 6 itu-r bt. 6 01-5 5 6 01 ? 18mhz 525 / 2:1 interla c e 3 6 2288 525 1920 1 6 9ne g ative 3 ne g ative 48 6s mpte 2 6 7m 6 ? 6 01 ? 18 mhz 6 25 / 2:1 interla c e 3 6 2304 6 25 1920 1 6 9ne g ative 2.5 ne g ative 57 6 itu-r bt. 6 01-5 7 720x48 6 /59.94/2:1 interla c e 54 3432 525 2880 252 ne g ative 3 ne g ative 48 6s mpte rp174 / s mpte 347m 8? 720x57 6 /50/2:1 interla c e 54 345 66 25 2880 252 ne g ative 2.5 ne g ative 57 6 itu-r bt.799 / s mpte 347m 9 720x483/59.94/1:1 pro g ressive 54 171 6 525 1440 127 ne g ative 6 ne g ative 483 s mpte 293m / s mpte 347m 10 720x57 6 /50/1:1 pro g ressive 54 1728 6 25 1440 127 ne g ative 5 ne g ative 57 6 itu-r bt.1358 / s mpte 347m 11* 1280x720/ 6 0/1:1 pro g ressive 74.25 1 6 50 750 1280 80 tri 5 ne g ative 720 s mpte 29 6 m 12* 1280x720/59.94/1:1 pro g ressive 74.175 1 6 50 750 1280 80 tri 5 ne g ative 720 s mpte 29 6 m
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 21 of 102 13* 1280/720/50/1:1 pro g ressive 74.25 1980 750 1280 80 tri 5 ne g ative 720 s mpte 29 6 m 14* 1280x720/30/1:1 pro g ressive 74.25 3300 750 1280 80 tri 5 ne g ative 720 s mpte 29 6 m 15* 1280x720/29.97/1:1 pro g ressive 74.175 3300 750 1280 80 tri 5 ne g ative 720 s mpte 29 6 m 1 6 * 1280x720/25/1:1 pro g ressive 74.25 39 6 0 750 1280 80 tri 5 ne g ative 720 s mpte 29 6 m 17* 1280x720/24/1:1 pro g ressive 74.25 4125 750 1280 80 tri 5 ne g ative 720 s mpte 29 6 m 18* 1280x720/23.98/1:1 pro g ressive 74.175 4125 750 1280 80 tri 5 ne g ative 720 s mpte 29 6 m 19* 1920x1035/ 6 0/2:1 interla c e 74.25 2200 1125 1920 80 tri 5 ne g ative 1035 s mpte 2 6 0m 20* 1920x1035/59.94/2:1 interla c e 74.175 2200 1125 1920 80 tri 5 ne g ative 1035 s mpte 2 6 0m 21* 1920x1080/ 6 0/1:1 pro g ressive 148.5 2200 1125 1920 80 tri 5 ne g ative 1080 s mpte 274m 22* 1920x1080/59.94/1:1 pro g ressive 148.35 2200 1125 1920 80 tri 5 ne g ative 1080 s mpte 274m 23* 1920x1080/50/1:1 pro g ressive 148.5 2 6 40 1125 1920 80 tri 5 ne g ative 1080 s mpte 274m 24* reserve d ? ? ? ??????? 25* 1920x1080/ 6 0/2:1 interla c e 74.25 2200 1125 1920 80 tri 5 ne g ative 1080 s mpte 274m 2 6 * 1920x1080/59.94/2:1 interla c e 74.175 2200 1125 1920 80 tri 5 ne g ative 1080 s mpte 274m table 1-2: recognized video standards (continued) vid_std [5:0] system nomenclature video pclk frequency (mhz) pclks / to t a l line to t a l l i n e s / frame pclks / active line h sync width (clocks) h sync polarity v sync width (lines) v sync polarity active lines / frame scan format standard
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 22 of 102 27* 1920x1080/50/2:1 interla c e 74.25 2 6 40 1125 1920 80 tri 5 ne g ative 1080 s mpte 274m 28* reserve d ? ? ? ??????? 29* 1920x1080/30/1:1 pro g ressive 74.25 2200 1125 1920 80 tri 5 ne g ative 1080 s mpte 274m 30* 1920x1080/30/psf 74.25 2200 1125 1920 80 tri 5 ne g ative 1080 s mpte rp 211 31* 1920x1080/29.97/1:1 pro g ressive 74.175 2200 1125 1920 80 tri 5 ne g ative 1080 s mpte 274m 32* 1920x1080/29.97/psf 74.175 2200 1125 1920 80 tri 5 ne g ative 1080 s mpte rp 211 33* 1920x1080/25/1:1 pro g ressive 74.25 2 6 40 1125 1920 80 tri 5 ne g ative 1080 s mpte 274m 34* 1920x1080/25/psf 74.25 2 6 40 1125 1920 80 tri 5 ne g ative 1080 s mpte rp 211 35* 1920x1080/24/1:1 pro g ressive 74.25 2750 1125 1920 80 tri 5 ne g ative 1080 s mpte 274m 3 6 * 1920x1080/24/psf 74.25 2750 1125 1920 80 tri 5 ne g ative 1080 s mpte rp 211 37* 1920x1080/23.98/1:1 pro g ressive 74.175 2750 1125 1920 80 tri 5 ne g ative 1080 s mpte 274m 38* 1920x1080/23.98/psf 74.175 2750 1125 1920 80 tri 5 ne g ative 1080 s mpte rp 211 * vid_ s td[5:0] = 2 an d 11-38 are re c o g nize d as input referen c es only. in a dd ition, vid_ s td[5:0] = 11-38 must b e ena b le d in the referen c e_ s tan d ar d _disa b le re g ister an d the hd_referen c e_ena b le b it of re g ister 82h[7] must b e set hi g h b efore they will b e re c o g nize d b y the d evi c e. ? when vid_ s td = 4, 6 , or 8, the v b lankin g output pulse wi d th is 2 lines too lon g for fiel d 1 an d 1 line too short for fiel d 2 when c ompare d to the d i g ital timin g d efine d in itu-r bt. 6 5 6 an d itu-r bt.799. table 1-2: recognized video standards (continued) vid_std [5:0] system nomenclature video pclk frequency (mhz) pclks / to t a l line to t a l l i n e s / frame pclks / active line h sync width (clocks) h sync polarity v sync width (lines) v sync polarity active lines / frame scan format standard
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 23 of 102 1.5 output timing signals table 1-3 describes the output timing signals available to the user via pins timing_out_1 to timing_out_8. the user may output any of the signals listed below on each pin by programming the output_selec t registers beginning at address 43h of the host interface. table 1-3: output timing signals signal name description default output pin h s yn c the h s yn c si g nal has a lea d in g e dg e at the start of the horizontal syn c pulse. its wi d th is d etermine d b y the sele c te d vi d eo stan d ar d (see ta b le 1-2 ). in g enlo c k mo d e the lea d in g e dg e of the output h s yn c si g nal is nominally simultaneous with the half amplitu d e point of the referen c e h s yn c input. this timin g may b e offset usin g the g enlo c k offset re g isters b e g innin g at a dd ress 1bh of the host interfa c e (see s e c tion 3.2.1.1 on pa g e 3 6 ). by d efault, after system reset, the polarity of the h s yn c si g nal output will b e a c tive low. the polarity may b e sele c te d as a c tive hi g h b y pro g rammin g the polarity re g ister at a dd ress 5 6 h of the host interfa c e (see s e c tion 3.10.3 on pa g e 6 7 ). timin g _out_1 h blankin g the h blankin g si g nal is use d to in d i c ate the portion of the vi d eo line not c ontainin g a c tive vi d eo d ata. the h blankin g si g nal will b e low ( d efault polarity) for the portion of the vi d eo line c ontainin g vali d vi d eo samples. the si g nal will b e low at the first vali d pixel of the line, an d hi g h after the last vali d pixel of the line. the h blankin g si g nal remains hi g h throu g hout the horizontal b lankin g perio d . the wi d th of this si g nal will b e d etermine d b y the sele c te d vi d eo stan d ar d (see ta b le 1-2 ). when in g enlo c k mo d e, the output h blankin g si g nal will b e phase lo c ke d to the referen c e h s yn c input. this timin g may b e offset usin g the g enlo c k offset re g isters b e g innin g at a dd ress 1bh of the host interfa c e (see s e c tion 3.2.1.1 on pa g e 3 6 ). the d efault polarity of this si g nal may b e inverte d b y pro g rammin g the polarity re g ister at a dd ress 5 6 h of the host interfa c e (see s e c tion 3.10.3 on pa g e 6 7 ). timin g _out_2 v s yn c the v s yn c timin g si g nal has a lea d in g e dg e at the start of the verti c al syn c pulse. its wi d th is d etermine d b y the sele c te d vi d eo stan d ar d (see ta b le 1-2 ). the lea d in g e dg e of v s yn c is nominally simultaneous with the lea d in g e dg e of the first b roa d pulse. when in g enlo c k mo d e, the output v s yn c si g nal will b e phase lo c ke d to the referen c e v s yn c input. this timin g may b e offset usin g the g enlo c k offset re g isters b e g innin g at a dd ress 1bh of the host interfa c e (see s e c tion 3.2.1.1 on pa g e 3 6 ). by d efault, after system reset, the polarity of the v s yn c si g nal output will b e a c tive low. the polarity may b e sele c te d as a c tive hi g h b y pro g rammin g the polarity re g ister at a dd ress 5 6 h of the host interfa c e (see s e c tion 3.10.3 on pa g e 6 7 ). timin g _out_3
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 24 of 102 v blankin g the v blankin g si g nal is use d to in d i c ate the portion of the vi d eo fiel d /frame not c ontainin g a c tive vi d eo lines. the v blankin g si g nal will b e low ( d efault polarity) for the portion of the fiel d /frame c ontainin g vali d vi d eo d ata, an d will b e hi g h throu g hout the verti c al b lankin g perio d . the wi d th of this si g nal will b e d etermine d b y the sele c te d vi d eo stan d ar d (see ta b le 1-2 ). when in g enlo c k mo d e, the output v blankin g si g nal will b e phase lo c ke d to the referen c e v s yn c input. this timin g may b e offset usin g the g enlo c k offset re g isters b e g innin g at a dd ress 1bh of the host interfa c e (see s e c tion 3.2.1.1 on pa g e 3 6 ). the d efault polarity of this si g nal may b e inverte d b y pro g rammin g the polarity re g ister at a dd ress 5 6 h of the host interfa c e (see s e c tion 3.10.3 on pa g e 6 7 ). note: when vid_ s td = 4, 6 , or 8, the v b lankin g output pulse wi d th is 2 lines too lon g for fiel d 1 an d 1 line too short for fiel d 2 when c ompare d to the d i g ital timin g d efine d in itu-r bt. 6 5 6 an d itu-r bt.799. timin g _out_4 f s yn c the f s yn c si g nal is use d to in d i c ate fiel d 1 an d fiel d 2 for interla c e d vi d eo formats. the f s yn c si g nal will b e hi g h ( d efault polarity) for the entire perio d of fiel d 1. it will b e low for all lines in fiel d 2 an d for all lines in pro g ressive s c an systems. the wi d th an d timin g of this si g nal will b e d etermine d b y the v s yn c parameters of the sele c te d vi d eo stan d ar d (see ta b le 1-2 ). the f s yn c si g nal always c han g es state on the lea d in g e dg e of v s yn c . when in g enlo c k mo d e, the output f s yn c si g nal will b e phase lo c ke d to the referen c e f s yn c input. this timin g may b e offset usin g the g enlo c k offset re g isters b e g innin g at a dd ress 1bh of the host interfa c e (see s e c tion 3.2.1.1 on pa g e 3 6 ). the d efault polarity of this si g nal may b e inverte d b y pro g rammin g the polarity re g ister at a dd ress 5 6 h of the host interfa c e (see s e c tion 3.10.3 on pa g e 6 7 ). timin g _out_5 f di g ital f di g ital is use d in d i g ital interla c e d stan d ar d s to in d i c ate fiel d 1 an d fiel d 2. the f di g ital c han g es state at the lea d in g e dg e of every v blankin g pulse. it will b e low ( d efault polarity) for the entire perio d of fiel d 1 an d for all lines in pro g ressive s c an systems. it will b e hi g h for all lines in fiel d 2 . the wi d th an d timin g of this si g nal will b e d etermine d b y the timin g parameters of the sele c te d vi d eo stan d ar d (see ta b le 1-2 ). when in g enlo c k mo d e, the output f di g ital si g nal will b e phase lo c ke d to the referen c e f s yn c input. this timin g may b e offset usin g the g enlo c k offset re g isters b e g innin g at a dd ress 1bh of the host interfa c e (see s e c tion 3.2.1.1 on pa g e 3 6 ). the d efault polarity of this si g nal may b e inverte d b y pro g rammin g the polarity re g ister at a dd ress 5 6 h of the host interfa c e (see s e c tion 3.10.3 on pa g e 6 7 ). timin g _out_ 6 table 1-3: output timing signals (continued) signal name description default output pin
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 25 of 102 10 fiel d i d entifi c ation the 10 fiel d i d entifi c ation (10fid) si g nal is use d to in d i c ate the 10-fiel d sequen c e for 29.97hz, 30hz, 59.94hz an d 6 0hz vi d eo stan d ar d s. it will b e low for output stan d ar d s with other frame rates. the sequen c e d efines the phase relationship b etween film frames an d vi d eo frames, so that c a d en c e may b e maintaine d in mixe d format environments. the 10fid si g nal will b e hi g h ( d efault polarity) for one line at the start of the 10-fiel d sequen c e. it will b e low for all other lines. the si g nal?s risin g an d fallin g e dg es will b e simultaneous with the lea d in g e dg e of the h s yn c output si g nal. alternatively, b y settin g b it 4 of the vi d eo_ c ontrol re g ister (see s e c tion 3.10.3 on pa g e 6 7 ), the 10fid output si g nal may b e c onfi g ure d to g o hi g h ( d efault polarity) on the lea d in g e dg e of the h s yn c output on line 1 of the first fiel d in the 10 fiel d sequen c e, an d b e reset low on the lea d in g e dg e of the h s yn c pulse of the first line of the se c on d fiel d in the 10 fiel d sequen c e. when in g enlo c k mo d e, the output 10fid si g nal will b e phase lo c ke d to the 10fid referen c e input. if a 10fid input is not provi d e d to the d evi c e, the user must c onfi g ure the 10fid output usin g re g ister 1ah of the host interfa c e (see s e c tion 3.8.1 on pa g e 58 ). for appli c ations involvin g au d io, this si g nal may b e use d in pla c e of the af s si g nal if the format sele c te d is appropriate for a 10 fiel d af s repetition rate, an d the d esire d phase relationship of au d io to vi d eo c lo c k phasin g c oin c i d es with the d esire d film frame c a d en c e. the d efault polarity of this si g nal may b e inverte d b y pro g rammin g the polarity re g ister at a dd ress 5 6 h of the host interfa c e (see s e c tion 3.10.3 on pa g e 6 7 ). please see s e c tion 3.8.1 on pa g e 58 for more d etail on the 10fid output si g nal. timin g _out_7 display ena b le the display ena b le (de) si g nal is use d to in d i c ate the d isplay ena b le for g raphi c d isplay interfa c es. this si g nal will b e hi g h ( d efault polarity) whenever pixel information is to b e d isplaye d on the d isplay d evi c e (i.e. whenever b oth h blankin g an d v blankin g are in the a c tive vi d eo state) the wi d th an d timin g of this si g nal will b e d etermine d b y the timin g parameters of the sele c te d vi d eo stan d ar d (see ta b le 1-2 ). the d efault polarity of this si g nal may b e inverte d b y pro g rammin g the polarity re g ister at a dd ress 5 6 h of the host interfa c e (see s e c tion 3.10.3 on pa g e 6 7 ). timin g _out_8 table 1-3: output timing signals (continued) signal name description default output pin
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 26 of 102 au d io frame s yn c ( gs 4901b only) the au d io frame s yn c (af s ) si g nal is hi g h ( d efault polarity) for the d uration of the first line of the n?th vi d eo frame to in d i c ate that the a c lk d ivi d ers are reset at the start of line 1 of that frame. it is d efine d a cc or d in g to the frame rate of the vi d eo format an d the sele c te d au d io sample rate pro g ramme d via the vid_ s td[5:0] an d a s r_ s el[2:0] pins or the host interfa c e. for example, if the vi d eo format is b ase d on a 59.94hz frame rate an d the au d io sample rate c lo c k is 48khz, then n=5, an d the af s si g nal will b e i d enti c al to the 10fid si g nal. by d efault, the af s si g nal is reset b y the 10 fiel d i d entifi c ation (10fid) referen c e input. this feature may b e d isa b le d usin g the au d io_ c ontrol re g ister at a dd ress 31h of the host interfa c e (see s e c tion 3.10.3 on pa g e 6 7 ). the af s si g nal may also b e reset usin g re g ister 1ah of the host interfa c e. with no referen c e, the frame d ivi d e b y ?n? c ontrollin g the af s si g nal will free-run at an ar b itrary phase. the d efault polarity of this si g nal may b e inverte d b y pro g rammin g the polarity re g ister at a dd ress 5 6 h of the host interfa c e (see s e c tion 3.10.3 ). please see s e c tion 3.8.2 on pa g e 59 for more d etail on the af s output si g nal. ? u s er_1~4 the gs 4901b/ gs 4900b offers four user pro g ramma b le output si g nals. ea c h u s er si g nal is c ontrolle d b y four timin g re g isters an d a polarity sele c t b it. the timin g re g isters d efine the start an d stop times in h pixels an d v lines an d b e g in at a dd ress 57h of the host interfa c e (see s e c tion 3.10.3 on pa g e 6 7 ). ea c h user si g nal is in d ivi d ually pro g ramma b le an d the polarity, position, an d wi d th of ea c h output may b e d efine d with respe c t to the h, v, an d f output timin g s of the d evi c e. ea c h output si g nal may b e pro g ramme d in b oth the horizontal an d verti c al d imensions relative to the lea d in g e dg es of h an d v s yn c . if d esire d , the pulses pro d u c e d may then b e c om b ine d with a lo g i c al and, or, or xor fun c tion to pro d u c e a c omposite si g nal (for example, a horizontal b a c k por c h pulse d urin g a c tive lines only, or the a c tive part of lines 15 throu g h 20 for verti c al information retrieval). ea c h output has sele c ta b le polarity. please see s e c tion 3.8.3 on pa g e 6 0 for more d etail on the u s er_1~4 output si g nals. ? table 1-3: output timing signals (continued) signal name description default output pin
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 27 of 102 2. electrical characteristics 2.1 absolute maximum ratings 2.2 dc electrical characteristics parameter conditions value/units s upply volta g e c ore an d analo g ( c ore_vdd, vid_pll_vdd, aud_pll_vdd, ph s _vdd, analo g _vdd) ? -0.3v to +2.1v s upply volta g e i/o (io_vdd, xtal_vdd) ? -0.3v to +3. 6 v input volta g e ran g e (any input) io_vdd = +3.3v -0.3v to +5.5v io_vdd = +1.8v -0.3v to +3. 6 v operatin g temperature ? -20 c < t a < 85 c s tora g e temperature ? -50 c < t s t g < 125 c s ol d erin g temperature ? 2 6 0 c e s d prote c tion on all pins ? 1 kv table 2-1: dc electrical characteristics v dd = 1.8v, t a = 0 c to 70 c , unless otherwise spe c ifie d . parameter symbol condition min typ max units notes system operatin g temperature ran g et a ? 0 25 70 c 1 c ore power supply volta g e c ore_vdd ? 1.71 1.8 1.89 v ? di g ital i/o buffer power s upply volta g e io_vdd 1.8v operation 1.71 1.8 1.89 v ? io_vdd 3.3v operation 3.135 3.3 3.4 6 5v ? vi d eo pll power s upply volta g e vid_pll_vdd ? 1.71 1.8 1.89 v ? au d io pll power s upply volta g e ( gs 4901b only) aud_pll_vdd ? 1.71 1.8 1.89 v ? analo g power s upply volta g e analo g _vdd ? 1.71 1.8 1.89 v ? c rystal buffer power s upply volta g e xtal_vdd 1.8v operation 1.71 1.8 1.89 v ? xtal_vdd 3.3v operation 3.135 3.3 3.4 6 5v ? vi d eo c lo c k phase s hift s upply volta g e ph s _vdd ? 1.71 1.8 1.89 v ?
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 28 of 102 gs 4901b power c onsumption (io_vdd = 1.8v nominal) p 1.8v rail max p c lk frequen c y ? 300 425 mw ? p 3.3v rail n/a n/a n/a mw ? p 1.8v rail p c lk = 27mhz ? 270 395 mw ? p 3.3v rail n/a n/a n/a mw ? gs 4901b power c onsumption (io_vdd = 3.3v nominal) p 1.8v rail max p c lk frequen c y ? 240 320 mw ? p 3.3v rail ? 90 170 mw ? p 1.8v rail p c lk = 27mhz ? 210 290 mw ? p 3.3v rail ? 90 170 mw ? gs 4900b power c onsumption (io_vdd = 1.8v nominal) p 1.8v rail max p c lk frequen c y ? 250 375 mw ? p 3.3v rail n/a n/a n/a mw ? p 1.8v rail p c lk = 27mhz ? 220 345 mw ? p 3.3v rail n/a n/a n/a mw ? gs 400b power c onsumption (io_vdd = 3.3v nominal) p 1.8v rail max p c lk frequen c y ? 190 270 mw ? p 3.3v rail ? 90 170 mw ? p 1.8v rail p c lk = 27mhz ?1 6 0 240 mw ? p 3.3v rail ? 90 170 mw ? digital i/o input volta g e, lo g i c low v il 1.8v operation ? ? 0.35 x vdd v? v il 3.3v operation ? ? 0.8 v ? input volta g e, lo g i c hi g hv ih 1.8v operation 0. 6 5 x io_vdd ?3. 6 v? v ih 3.3v operation 2.145 ? 5.25 v ? output volta g e, lo g i c low v ol c urrent d rive = hi g h or low as sele c te d ??0.4v2 output volta g e, lo g i c hi g hv oh c urrent d rive = hi g h or low as sele c te d 0. 6 5 x io_vdd ??v 2 digital output currents table 2-1: dc electrical characteristics (continued) v dd = 1.8v, t a = 0 c to 70 c , unless otherwise spe c ifie d . parameter symbol condition min typ max units notes
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 29 of 102 timin g output drive c urrent ? io_vdd = 1.8v c urrent d rive = low ?5?ma? ? io_vdd = 3.3v c urrent d rive = low ?10?ma? ? io_vdd = 1.8v c urrent d rive = hi g h ?7?ma? ? io_vdd = 3.3v c urrent d rive = hi g h ?14?ma? c lo c k output drive c urrent ? io_vdd = 1.8v c urrent d rive = low ?5?ma? ? io_vdd = 3.3v c urrent d rive = low ?7?ma? ? io_vdd = 1.8v c urrent d rive = hi g h ?7?ma? ? io_vdd = 3.3v c urrent d rive = hi g h ?14?ma? output volta g e lvd s , c ommon mo d e v o c m ? 1.125 1.25 1.375 v 3 output volta g e lvd s , differential v odiff ? ? 350 ? mv 3 lvd s hi g h-impe d an c e leaka g e c urrent ? to 1.8v or g nd ? ? 1.4 ua ? note s 1. all dc and ac electrical parameters within specification. 2. assuming that the current being sourced or sinked is less than the timing output drive current specified. 3. into a 100 termination connected between pclk3 and pclk3 . table 2-1: dc electrical characteristics (continued) v dd = 1.8v, t a = 0 c to 70 c , unless otherwise spe c ifie d . parameter symbol condition min typ max units notes
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 30 of 102 2.3 ac electrical characteristics table 2-2: ac electrical characteristics v dd = 1.8v, t a = 0 c to 70 c , unless otherwise spe c ifie d . parameter symbol condition min ty p max units notes system referen c e dete c tion time ? from when the referen c e input is first present ? 2 4 frames ? digital i/o p c lk output frequen c y ? ? 3.375 ? 1 6 5mhz? p c lk j itter ? xtal_vdd = 3.3v ? 350 ? ps 1, 2 p c lk duty c y c le ? ? 40 ? 6 0%? p c lk1 & p c lk2 rise/fall times 15pf loa d 20% - 80% ? io_vdd = 1.8v c urrent d rive = low ??1.7ns? ? io_vdd = 3.3v c urrent d rive = low ??1.5ns? ? io_vdd = 1.8v c urrent d rive = hi g h ??1.1ns? ? io_vdd = 3.3v c urrent d rive = hi g h ??0.9ns? p c lk3 rise/fall time 20% - 80% ? 100 d ifferential loa d 10pf to g roun d per pin ? ? 850 ps ? p c lk outputs relative timin g s kew ? d efault p c lk phase d elay of zero -3 ? 3 ns 3 a c lk frequen c y ( gs 4901b only) ? ? 0.0097 ? 49.152 mhz ? a c lk duty c y c le ( gs 4901b only) ?? 40? 6 0%4 a c lk1-3 rise/fall times 15pf loa d 20% - 80% ( gs 4901b only) ? io_vdd = 1.8v c urrent d rive = low ??3.0ns? ? io_vdd = 3.3v c urrent d rive = low ??1.5ns? ? io_vdd = 1.8v c urrent d rive = hi g h ??2.5ns? ? io_vdd = 3.3v c urrent d rive = hi g h ??1.4ns? a c lk outputs relative timin g s kew ( gs 4901b only) ?? -3?3ns3
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 31 of 102 fi g ure 2-1: p c lk to timin g _out s i g nal output timin g di g ital timin g output delay time t od ???4.3ns5 di g ital timin g output hol d time t oh ?1??ns5 di g ital timin g output rise/fall times 15pf loa d 20% - 80% ? io_vdd = 1.8v c urrent d rive = low ??3.0ns? ? io_vdd = 3.3v c urrent d rive = low ??1.5ns? ? io_vdd = 1.8v c urrent d rive = hi g h ??2.5ns? ? io_vdd = 3.3v c urrent d rive = hi g h ??1.4ns? gspi gs pi input c lo c k frequen c yf gs pi ? ? ? 10.0 mhz 6 gs pi c lo c k duty c y c le d c gs pi ?40? 6 0% 6 gs pi input s etup time t 3 in fi g ure 3-15 ?1.5??ns 6 gs pi input hol d time t 8 in fi g ure 3-15 ?1.5??ns 6 note s 1. the video output clock may be directly connected to gennums gs9062 serializer for a smpte-compliant sdi output with output j itter below 0.2ui. 2. all output standards except vid_std[5:0] = 1 (450ps typ.) and vid_std[5:0] = 5 or 6 (500ps typ.) 3. timings from any clk output to any other clk output. 4. if fs=96khz and aclk is configured to output a clock signal at 192fs or 384fs, a 512fs clock w ill typically have a 33% duty c ycle distortion. see section 3.7.2 on page 54 . 5. with pclk phasing delay set to nominal (zero offset), each in crement of the clock phasing adjustment decreases output hold ti me and delay time by a nominal 700ps. the times t od and t oh are defined in figure 2-1 . 6. for detailed gspi timing pa rameters, please refer to table 3-12 . table 2-2: ac electrical characteristics (continued) v dd = 1.8v, t a = 0 c to 70 c , unless otherwise spe c ifie d . parameter symbol condition min ty p max units notes 50 % t oh t od v oh v ol v oh v ol timing_out pclk
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 32 of 102 table 2-3: suggested external crystal specification 27.000000 mhz at c ut nominal dissipation = 50 uw frequen c y a cc ura c y at 25 c = +/- 10ppm frequen c y variation 0-70 c = +/- 10ppm a s r = 50 +/- 20 note: the user may sele c t an appropriate c rystal a cc ura c y for their appli c ation. if the d evi c e is operatin g in free run mo d e, the output c lo c k an d timin g si g nals will have the same a cc ura c y as the c rystal. however, if operatin g in g enlo c k mo d e, all output si g nals are b ase d on the input referen c e, an d therefore a less a cc urate c rystal may b e suffi c ient. s ee s e c tion 3.2 on pa g e 35 .
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 33 of 102 2.4 solder reflow profiles the device is manufactured with matte-sn terminations and is compatible with both standard eutectic and pb-free solder reflow profiles. msl qualification was performed using the maximum pb-free reflow profile shown in figure 2-2 . the recommended standard pb reflow profile is shown in figure 2-3 . fi g ure 2-2: maximum p b -free s ol d er reflow profile (preferre d ) fi g ure 2-3: s tan d ar d p b s ol d er reflow profile 25c 150c 200c 217c 260c 250c time temperature 8 min. max 60-180 sec. max 60-150 sec. 20-40 sec. 3c/sec max 6c/sec max 25c 100c 150c 183c 230c 220c time temperature 6 min. max 120 sec. max 60-150 sec. 10-20 sec. 3c/sec max 6c/sec max
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 34 of 102 3. detailed description 3.1 functional overview the gs4901b/GS4900B is a highly flexible, digitally controlled clock synthesis circuit and timing generator with genlock capability. the device has two main modes of operation: genlock mode and free run mode. in genlock mode, the video clock and timing outputs, will be frequency and phase locked to the detected reference input signal. in free run mode, the occurrence of all frequencies is based on a 27mhz external crystal reference. the gs4901b/GS4900B will recognize input reference signals conforming to 36 different video standards. it supports cross-lock ing, allowing the output to be genlocked to an incoming reference that is different from the output video standard selected. when the device is in genlock mode and the input reference is removed, the gs4901b/GS4900B will enter freeze mode. in this mode, the output clock and timing signals will maintain their previously genlocked phase and frequency to within +/- 2ppm. the user may select to output one of 4 different video sample clock rates. the chosen clock frequency may be further internally divided, and is available on two video clock outputs and one lvds video clock output pair. the video clocks may also be individually phase delayed with respect to the timing outputs for clock skew control. eight user-selectable timing outputs are provided that can automatically produce the following timing signals for 9 different vi deo formats: hsync, hblanking, vsync, vblanking, f sync, f digital, afs (gs4901b only), de, and 10fid. in addition, the gs4901b provides three audio sample clock outputs that can produce audio clocks up to 512fs with fs ranging from 9.7khz to 96khz. audio to video phasing is accomplished by either an external 10fid input reference, a 10fid signal specified via internal registers, or a user-programmed audio frame sequence. 3.2 modes of operation the gs4901b/GS4900B will operate in either genlock mode or free run mode depending on the setting of the genlock pin. these two modes are described in section 3.2.1 on page 35 and section 3.2.2 on page 39 respectively. if desired, the external genlock pin may be ignored by setting bit 5 of the genlock_control register (address 16h) so that genlock can instead be controlled via the host interface (see section 3.10.3 on page 67 ). although the external genlock pin will be ignored in this case, it should not be left floating. 3.2.1 genlock mode when the application layer sets the genlock pin low and the device has successfully genlocked the outputs to the input reference, the gs4901b/GS4900B will enter genlock mode. in this mode, all clock and timing generator outputs will be frequency and phase
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 35 of 102 locked to the detected input reference signal. the pclk outputs will be locked to the h reference. when in genlock mode, the output clock and timing signals are generated using the applied reference signal. the 27mhz crystal reference is necessary for operation; however, neither crystal accuracy nor changes in crystal frequency (due to a shift in operating temperature) will affect the output signals. for example, the output signals will be generated with the same accuracy whether the 27mhz reference crystal has an accuracy of 10ppm or 100ppm. the gs4901b/GS4900B supports cross-locking, allowing the outputs to be genlocked to an incoming reference that is different from the output video standard selected (see section 3.6 on page 47 ). note: the user must apply a reference to the input of the device prior to setting genlock = low. if the genlock pin is set low and no reference signal is present, the generated clock and timing outputs of the device may correspond to the internal default settings of the chip until a reference is applied. 3.2.1.1 genlock timing offset by default, the phase of the clock and timing out signals is genlocked to the input reference signal. these output signals may be phase adjusted with respect to the input reference by programming the host interface (see section 3.10.3 on page 67 ). offsets are separately programmable in terms of clock phase, horizontal phase, and vertical phase (i.e. fractions of a pixel, pixels, and lines). genlock timing offsets can be used to co-time the output of a piece of equipment containing the gs4901b/GS4900B with the outputs of other equipment at different locations. the signal leaving the piece of equipment containing the gs4901b/GS4900B may pass through processing equipment with significant fixed delays before arriving at the switcher. these delays may include video line delays or even field delays. to compensate for these delays, genlock timing offsets allow the user to back-time the output of the equipment relative to the input reference. using the host interface, the following registers may be programmed once the device is stably locked: ? clock_phase_offset (1dh) - with a range of zero to one clock pulse in increments of between 1/128 and 1/512 of a clock period (depending on the pclk frequency). the increments will be between 100ps and 150ps. all clock and timing output signals will be delayed by the clock phase offset programmed in this register. ? h_offset (1bh) - the difference between the reference hsync signal and the output h sync and/or h blanking signal in clock pulses, with a control range of zero to +1 line. all timing output signals will be delayed by the horizontal offset programmed in this register. ? v_offset (1ch) - the difference between the reference vsync signal and the output v sync and/or v blanking in lines, with a control range of zero to +1 frame. all line-based timing output signals will be delayed by the vertical offset programmed in this register.
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 36 of 102 the encoding scheme for the clock_phase_offset register (1dh) is shown in table 3-1 . the offset programmed will be in the positive direction. note that the step size will depend on the frequency of the output video clock. the value programmed in the h_offset register (1bh) must not exceed the maximum number of clock periods per line of the outgoing video standard. similarly, the value programmed in the v_offset register (1ch) must not exceed the maximum number of lines per frame of the outgoing standard. both horizontal and vertical offsets will be in the positive direction. negative offsets (advances) are achieved by programming a value in the appropriate register equal to the maximum allowable offset minus the desired advance. notes: 1. the device will delay all output timing signals by 2 pclks relative to the input hsync reference. this will occur even when the h_offset register is not programmed. the user may compensate for this delay by subtracting 2 pclk cycles from the desired horizontal offset before loading the value into the host interface. 2. for both sync and blanking-based input references, the device will advance all line-based output timing signals by 1 line relative to the input vsync reference for all output standards except vid_std[5:0] = 4, 6, and 8. this will occur even when the v_offset register is not programmed. the user may compensate for this advance by adding 1 line to the desired vertical offset before loading this value into the register. table 3-1: clock_phase_offset [15:0] encoding scheme vid_std[5:0] setting output video clock frequency step size (fraction of a pclk) maximum number of steps bits required to set the number of steps clock_phase_offset [15:0] settings 1 f p c lk < 20mhz 511 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 8 000001 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 3- 6 20mhz < f p c lk < 40mhz 255 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 7 000010 b 7 b 6 b 5 b 4 0 b 3 b 2 b 1 b 0 7-10 40mhz < f p c lk < 54mhz 127 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 6 000100 b 6 b 5 b 4 00 b 3 b 2 b 1 b 0 note: pro g ram c lo c k_phase_offset = 0000 0000 0000 0000 b to a c hieve a zero c lo c k phase offset. 1 512 - - - - - - - - - 1 256 - - - - - - - - - 1 128 - - - - - - - - -
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 37 of 102 3. when locking the 525-line sd output standards to the ?f/1.001? hd input reference standards, the device will delay all li ne-based output timing signals by vsync lines relative to the input vsync reference. this will occur even when the v_offset register is not programmed. the user may compensate for this delay by subtracting vsync lines from the desired vertical offset before loading this value into the register. the value vsync is given by the equation: where: hsync_in_period = the period of the h reference pulse vsync_hsync = the time difference between the leading edges of the applied v and h reference pulses hsync_out_period = the period of the generated h sync output see figure 3-1 . h_feedback_divide represents the numerator of the ratio of the output clock frequency to the frequency of the h reference pulse. fi g ure 3-1: s d-hd c al c ulation 4. for sync-based input references, the device will advance all line-based output timing signals by 1 line if the value programmed in the h_offset register is greater than 20. the user may compensate for this advance by adding 1 line to the desired vertical offset before loading this value into the register. in addition, the internal v_lock and f_lock signals reported in bits 3 and 4 of register 16h will be low when h_offset = 20 only, although the device will remained genlocked. the user may choose to mask these lock signals such that the device will continue to report genlock under this condition. vsync hsync_i n_peri od vsync _h syn c 2 ( hsync_out_peri od ) ? + = h s yn c v s yn c h s yn c v s yn c d v s yn c _h s yn c h s yn c _out_perio d h s yn c _in_perio d d v s yn c
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 38 of 102 5. for blanking-based input references, the device will advance all line-based output timing signals by 1 line if the value programmed in the h_offset register is greater than the number of output video clock cycles from the start of h sync to the end of active video (hsync_to_eav) + 20. the value of hsync_to_eav is reported in register 51h and changes according to the output vid_std selected. the user may compensate for this advance by adding 1 line to the desired vertical offset before loading this value into the register. in addition, the internal v_lock and f_lock signals reported in bits 3 and 4 of register 16h will be low when h_offset = hsync_to_eav + 20 only, although the device will remained genlocked. the user may choose to mask these lock signals such that the device will continue to report genlock under this condition. 6. the offsets that occur as described in notes 1-5 are independent of one another and must be accounted for as such. 3.2.1.2 freeze mode when the device is in genlock mode and the input reference is removed, the gs4901b/GS4900B will enter freeze mode. the behaviour of the device during loss and re-acquisition of an input reference signal is described in section 3.5.3 on page 45 . in freeze mode, the frequency of the output clock and timing signals will be maintained to within +/- 2ppm. this assumes a loop bandwidth of 10hz. also, if the frequency of the 27mhz reference crystal shifts while in freeze mode, the frequency of the output clock and timing signals will shift as well. 3.2.2 free run mode the gs4901b/GS4900B will enter free run mode when the genlock pin is set high by the application layer. in this mode, the occurrence of all frequencies is based on the external 27mhz reference input. therefore, the frequency of the output clock and timing signals will have the same accuracy as the crystal reference. if operating in free run mode, using a more accurate crystal (e.g. 10ppm) ensures more accurate clock and timing signals are generated. note: in free run mode, the audio clocks of the gs4901b will remain genlocked to the video clock. figure 3-2 summarizes the differences in output accuracy in each mode of operation. assuming a crystal reference of +/-100ppm, in free run mode the frequency of the output clock and timing signals will be as accurate as the crystal. in genlock mode the frequency will be as accurate as the input reference regardless of the crystal accuracy. in freeze mode, the frequency of the output clock and timing signals will be maintained to within +/- 2ppm.
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 39 of 102 fi g ure 3-2: output a cc ura c y an d mo d es of operation 3.3 output timing format selection at device power-up (described in section 3.12 on page 94 ), the application layer should immediately set the external vid_std[5:0] and asr_sel[2:0] pins. the vid_std[5:0] pins are used to select a pre-programmed output video format. the asr_sel[2:0] pins are only available on the gs4901b, and are used to select the fundamental audio frequency or to turn off audio clock generation. the output timing formats selectable by the user via the vid_std[5:0] pins are listed in section 1.4 on page 19 . table 3-7 in section 3.7.2 on page 54 lists the audio sample rates available via the asr_sel[2:0] pins. note: the vid_std[5:4] pins should be grounded by the application layer since these pins are not required to select output video standards 1 to 10. on power-up, the device will first check the status of the genlock pin. if genlock is set low and a valid reference has been applied to the inputs, the device will output the selected video standard while attempting to genlock. however, if a reference signal has not been applied and genlock =low, the initial clock and timing outputs may be determined by the internal default settings of the chip. if genlock is set high, the device will immediately enter free run mode and will correctly output the selected video standard. when operating in free run or genlock mode, the gs4901b/GS4900B will continuously monitor the settings of the vid_std[5:0] and asr_sel[2:0] pins. if the user wishes to change the format of the output clocks and timing signals, these pins may be reconfigured at any time, although it is recommended that the device be reset when changing output video standards. free run genlock freeze 27 mhz -2ppm no input reference reference applied reference lost time assumption: reference xtal is 27mhz+/-100ppm -100ppm +100ppm +2ppm + notes: 1. t represents the temperature variability of the crystal 2. diagram not to scale. t t - t + t - t
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 40 of 102 3.4 input reference signals the hsync, vsync, fsync, and 10fid reference signals are applied to the gs4901b/GS4900B via the designated input pins. to operate in genlock mode, the input refere nce signals must be valid and must conform to a recognized video standard (see section 3.5 on page 43 ). in free run mode, no input reference is required. section 3.4.1 on page 41 describes the hsync, vsync and fsync input timing. the 10fid input signal is discussed in section 3.4.2 on page 42 . 3.4.1 hsync, vsync, and fsync the hsync, vsync, and fsync input reference signals may have analog timing, such as from gennum?s gs4981/82 sync separators ( figure 3-3 ), or may have digital timing, such as from gennum?s gs 1559/60a/61 deserializers ( figure 3-4 ). section 1.4 on page 19 lists the 36 pre-programmed video timing formats recognized by the gs4901b/GS4900B. if the input reference format does not include an f sync signal, the fsync pin should be held low. fi g ure 3-3: example h s yn c , v s yn c , an d f s yn c analo g input timin g from a s yn c s eparator fi g ure 3-4: example h blankin g , v blankin g , an d f di g ital input timin g from an s di deserializer hsync vsync fsync h:v:f timing - hd 20-bit output mode pclk luma data out chroma data out h xyz (eav) 000 000 3ff 000 000 3ff v f 000 000 3ff 000 000 3ff xyz (eav) xyz (sav) xyz (sav) h signal timing typical h timing alternative h timing
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 41 of 102 3.4.2 10fid the 10fid input is a reset pin, which can be used to reset the divider for the 10fid output signal. in the gs4901b, the 10fid input pin will also reset the divider for the afs output signal. this default setting may be modified using the audio_control register of the host interface (see section 3.10.3 on page 67 ). the gs4901b will reset the phase of the audio clocks to the leading edge of the h sync output on line 1 of every output frame in which the 10fid input is high. if the input reference format does not include a 10 field id signal, the external 10fid input pin should be held low. the timing of the 10fid input signal is shown in figure 3-5 . fi g ure 3-5: 10fid input timin g 3.4.3 automatic polarity recognition to accommodate any standards that employ the polarity of the h and v sync signals to indicate the format of the display, the gs4901b/GS4900B will recognize h and v sync polarity and automatically synchronize to the leading edge. the polarities of the hsync and vsync signals are reported in bits 3 and 4 of the video_status register. additionally, bit 2 of this register reports the detection of either analog or digital input timing. see section 3.10.3 on page 67 for detailed register descriptions. 10fid input horizontal sync input total line line 1, frame 1 every 'n' frames line 1 every n frames where: n = 5 @ 29.97 fps, 30 fps n = 10 @ 59.94 fps, 60 fps
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 42 of 102 3.5 reference format detector the reference format detector checks the validity and analyzes the format of the input reference signal. it is designed to accurately differentiate between 59.94 and 60hz frame rates. as described in section 1.4 on page 19 , the gs4901b / GS4900B will automatically recognize the sd video standards defined by vid_std[5:0] = 1 to 10. however, in order to enable the device to recognize and lock to any of the hd reference formats defined by vid_std[5:0] = 11 to 38, the user must set the corresponding bit low in the reference_standard_disable register, located at address 11h-13h of the host interface. the user must also set the hd_reference_enable bit of register 82h[7] high. see the description of the reference_standard_disable and hd_reference_enable registers in section 3.10.3 on page 67 . 3.5.1 horizontal and vertical timing characteristic measurements when a reference signal is applied to the designated input pins, the gs4901b/GS4900B will analyse the signal and report the following in registers 0ah to 0eh of the host interface: ? the number of 27mhz clock pulses between leading edges of the h input reference signal (h_period register) ? the number of 27mhz clock pulses in 16 horizontal periods (h_16_period register) ? the number of h reference pulses between leading edges of the v input reference signal (v_lines register) ? the number of h reference pulses in two vertical periods (v_2_lines register) ? the number of h reference pulses in one f period (f_lines register) these parameters may be read via the host interface and are used by the device to determine reference signal validity.
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 43 of 102 3.5.2 input reference validity before the device attempts to operate in genlock mode, the input signals applied to hsync and vsync must be valid (sd references only) and must conform to one of the recognized and enabled video standards, as described in section 1.4 on page 19 . for an sd input reference signal to be considered valid, the periodicity of hsync must be between 29.66us and 70us, and the period icity of vsync must be between 16ms and 25ms. the fsync signal is not essential for validity. the ref_lost pin will be set low once the sd input reference signal is determined to be valid. for hd input reference signals where the user has set the hd_reference_enable bit of register 82h[7] high, the device will not measure signal validity. in this case, the ref_lost pin will be low whenever any reference signal is present on the input. the device then compares the timing parameters of the input reference signal to each of the video standards that has been enabled in the the reference_standard_disable register (there may be up to 36 video standards if all hd standards are enabled). the device will then determine if the input reference is one of the enabled and recognized standards. if it is, the vid_std[5:0] value for the format is written to the input_standard register at address 0fh of the host interface. if the reference format is unrecognized or disabled, 00h is programmed in this register. once a reference signal is recognized by the device, vsync and fsync will no longer be monitored. loss of signal on these pins will not affect the operation of the device. if the ref_lost pin is high, or if the input signal is unrecognized as one of the enable video formats, the genlock pin should not be set low. the ref_lost output pin may also be read via bit 0 of the genlock_status register (see section 3.10.3 on page 67 ). 3.5.2.1 ambiguous standard selection there are some standards with identical h, v, and f timing parameters, such that the gs4901b/GS4900B?s reference format detector cannot distinguish between them. table 3-2 groups standards with shared h, v, and f periods. using the amb_std_sel register at address 10h of the host interface, the user may select their choice of standard to be identified with a particular set of measurements. for example, to have 1716 clocks of 27mhz per line with 525 lines per frame identified as 4fsc 525, program amb_std_sel[10:0] = xxx10xxxxxx, where ?x? signifies ?don?t care?.
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 44 of 102 3.5.3 behaviour on loss and re-acquisition of the reference signal by default, the gs4901b/GS4900B will ignore one missing h pulse on the hsync pin and will continue to operate in genlock mode (although the lock_lost pin will temporarily be set high). this behaviour is controlled by the run_window bits of register address 24h. if there are two consecutive missing h pulses on the hsync input pin, the ref_lost and lock_lost pins will both go high and the device will enter freeze mode. an table 3-2: ambiguous standard identification number standard h (27mhz clocks) 16_h (27mhz clocks) v (lines) f (lines) amb_std_sel[10:0] 1 1920x1080/ 6 0/2:1 interla c e (25) 800 12800 5 6 2.5 1125 x x x x x x x x x 0 0 1920x1080/30/psf (30) 800 12800 5 6 2.5 1125 x x x x x x x x x 0 1 1920x1035/ 6 0/2:1 interla c e (19) 800 12800 5 6 2.5 1125 x x x x x x x x x 1 0 2 1920x1080/59.94/2:1 interla c e (2 6 ) 800.8 12813 5 6 2.5 1125 x x x x x x x 0 0 x x 1920x1080/29.97/psf (32) 800.8 12813 5 6 2.5 1125 x x x x x x x 0 1 x x 1920x1035/59.94/2:1 interla c e (20) 800.8 12813 5 6 2.5 1125 x x x x x x x 1 0 x x 3 1920x1080/50/2:1 interla c e (27) 9 6 0153 6 05 6 2.4 1125 x x x x x 0 0 x x x x 1920x1080/25/psf (34) 9 6 0153 6 05 6 2.4 1125 x x x x x 0 1 x x x x 4 6 01 525 / 2:1 interla c e (3) 171 6 2745 6 2 6 2.5 525 x x x 0 0 x x x x x x 720x48 6 /59.94/2:1 interla c e (7) 171 6 2745 6 2 6 2.5 525 x x x 0 1 x x x x x x 4fs c 525 / 2:1 interla c e (1) 171 6 2745 6 2 6 2.5 525 x x x 1 0 x x x x x x 6 01 - 18mhz 525/2:1 interla c e (5) 171 6 2745 6 2 6 2.5 525 x x x 1 1 x x x x x x 5 6 01 6 25 / 2:1 interla c e (4) 1728 27 6 48 312.5 6 25 x 0 0 x x x x x x x x 720x57 6 /50/2:1 interla c e (8) 1728 27 6 48 312.5 6 25 x 0 1 x x x x x x x x c omposite pal 6 25/2:1/25 (2) 1728 27 6 48 312.5 6 25 x 1 0 x x x x x x x x 6 01 - 18mhz 6 25/2:1 interla c e ( 6 ) 1728 27 6 48 312.5 6 25 x 1 1 x x x x x x x x 6 r s vd r s vd r s vd r s vd r s vd 0 x x x x x x x x x x 720x483/59.94/1:1 pro g ressive (9) 858 13728 525 525 1 x x x x x x x x x x ?x? si g nifies ? d on?t c are.? the x b it will b e i g nore d when d eterminin g whi c h stan d ar d to sele c t in ea c h of the 6 g roups a b ove. note: when the s d input referen c e format of 720x483/59.94/1:1 (vid_ s td = 9) is applie d to the input, the user must set b it [15] of the of the am b _ s t d _ s el re g ister a dd ress to ' 1 ' b efore the d evi c e will re c o g nize this referen c e.
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 45 of 102 internal flywheel ensures the selected output clock and timing signals maintain their previous phase and frequency and continue to operate without glitches. the vsync and fsync signals are not monitored in genlock mode; loss of signal on these pins will not affect the operation of the device. note 1: if the input reference is removed and re-applied, all line-based timing outputs will be inaccurate for up to on e frame for all output standards. note 2: when locking the sd input reference standards 3, 5, 7, or 9 to the ?f/1.001? hd input reference standards, there may be a random phase difference between the input vsync and output v sync signals occuring each time the input reference is removed and re-applied. this will affect all line-bas ed timing outputs. the user may reset the line-based counters after the reference is re-applied without disrupting the pixel or audio clocks by toggling bit 15 of register address 83h in the host interface. this will cause the input vsync and line-based timing output signals to take on their default timing relationship, as described in note 3 of section 3.2.1.1 on page 36 . re-acquisition of the same reference upon re-application of the reference signal, the device checks whether the reference has drifted more than +/- 2us from its expected location by comparing the current relative position of the h pulses with the previous position, over a 16-line interval. if the reference returns with the h pulses in the expected location +/- 2us, the pll will drift lock and the clock generator will continue to operate without a glitch. the ref_lost and lock_lost pins will be set back low. if the reference returns with the h pulses outside the +/- 2us window, the device will crash lock the output timing to the new input phase. the principles of crash lock and drift lock are described in section 3.6.1 on page 49 . note: to resume proper genlock operation upon re-application of the reference signal, the user must implement the following register manipulation every time the reference is removed and re-applied: 1. read the value contained in register address 24h 2. clear the run_window bits [2:0] of register 24h 3. re-write the value read in step 1 to register address 24h. this procedure will force the device to lock to the reference as described above, but will maintain the flywheeling capability of the gs4901b/GS4900B should a single missing h pulse occur in the genlocked state. to avoid the above procedure, the user may choose to clear the run_window bits [2:0] of register address 24h upon power-up or reset. however, this will disable the flywheeling feature of the device that allows it to maintain genlock through one missing input h pulse.
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 46 of 102 acquisition of a new reference when a new reference is applied, the device continues to operate in freeze mode while the reference format detector checks for validity as described in section 3.5.2 on page 44 . once validity is detected, the ref_lost pin is set low. assuming genlock is low, the device will then attempt to genlock the selected output clock and timing signals to the new input reference. if the output can be automatically genlocked to the new input reference, lock_lost will go low and the device will re-enter genlock mode. otherwise, the lock_lost pin will remain high and the device will enter free run mode. 3.5.4 allowable frequency drift on the reference by default, the frequency of the reference h pulse on hsync may drift from its expected value by approximately +/- 0.2% before the internal video pll loses lock. this tolerance may be adjusted using the max_ref_delta register at address 1eh of the host interface. the encoding scheme is shown in table 3-3 . the default value of the register is bh. note: regardless of the setting of this register, the device will always differentiate between 59.94hz and 60hz reference standards. 3.6 genlock when both the ref_lost output and the genlock input are low, the device will attempt to genlock the output clock and timing signals to the input reference. note: the user must apply a reference to the input of the device prior to setting genlock = low. if the genlock pin is set low and no reference signal is present, the table 3-3: max_ref_delta encoding scheme register setting maximum allowable frequency drift register setting maximum allowable frequency drift 0h +/- 2 -20 8h +/- 2 -12 1h +/- 2 -19 9h +/- 2 -11 2h +/- 2 -18 ah +/- 2 -10 3h +/- 2 -17 bh +/- 2 -9 4h +/- 2 -1 6 c h +/- 2 -8 5h +/- 2 -15 dh +/- 2 -7 6 h +/- 2 -14 eh +/- 2 - 6 7h +/- 2 -13 fh +/- 2 -5 the maximum allowa b le frequen c y d rift is measure d as a fra c tion of the frequen c y of the referen c e h pulse.
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 47 of 102 generated clock and timing outputs of the device may correspond to the internal default settings of the chip until a reference is applied. once reference validity is established and the reference format is recognized, the device uses an internal cross-reference genlock look-up table to determine whether the input can be used to genlock the output. a simplified version of this look-up table is shown in table 3-4. the table represents a matrix with the vid_std[5:0] number representation of each possible reference format along the top axis, and the vid_std[5:0] representation of each possible output timing format along the vertical axis. a shaded box indicates that the output format can be automatically genlocked to the input reference. if the device determines that the output can be automatically genlocked to the input reference, it will lock the output format to the reference, adjust the output timing signals based on the genlock timing offset registers (section 3.2.1.1 on page 37), and then set the lock_lost pin low. if the device cannot automatically genlock the output to the applied reference, the lock_lost pin will be set high and the device will operate in free run mode. individual h, v, and f-locked signals can be read from the genlock_status register of the host interface. additionally, designated bits in the genlock_control register may be configured to permit the genlock block to ignore invalid timing on the hsync, vsync, or fsync pin when determining the locked status of the device. these registers are described in section 3.9.3 on page 66. the user may disable one or more of the 36 video standards listed in table 1-2 from being used to genlock the output by setting the reference_standard_disable register located at address 11h-13h of the host interface. if a reference is applied that is disabled in the reference_standard_disable register, the lock process will fail when the application layer sets genlockb = low. note: if the device is already genlocked to an input reference and the applied standard is subsequently disabled in the reference_standard_disable register, the device will remain locked. by default, the hd video reference formats are disabled in the reference_standard_disable register and so must be enabled by the user before attempting to lock to an hd reference. see section 1.4 on page 19 . table 3-4: cross-reference genlock table input referen c e format 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 6 17 18 19 20 21 22 23 25 2 6 27 29 30 31 32 33 34 35 3 6 37 38 1 3 4 5 6 7 8 9 10
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 48 of 102 3.6.1 adjustable locking time the gs4901b/GS4900B offers two different locking mechanisms to allow the user to control the pll lock time and the integrity of the output signal during the locking process. the locking process is said to take place after the application of the input reference and before the lock_lost signal is set low. by default, the internal pll will crash lock. this locking process will ensure a minimum pll locking time; however, crash lock will cause the phase of the output clock and timing signals to jump during the locking process. the crash behaviour of the video pll is controlled by the crash_time bits of register address 24h. alternatively, the user may set bit 1 of register 16h high to force the pll to drift lock. drift lock will increase the locking time of the pll, but will maintain the signal integrity of the output clock and timing pulses during the locking process. as discussed in section 3.5.3 on page 45 , the device will normally drift lock when the reference is removed and subsequently re-applied during genlock mode. 3.6.2 adjustable loop bandwidth the default loop bandwidth of the gs4901b/GS4900B's internal video pll is 10hz when the output video standard is the same as the input reference format. for other cross-locking combinations, the default loop bandwidth may be smaller than 1hz or as large as 30hz. the user may adjust the loop bandwidth of both the video and audio plls depending on the input, output, and audio standards selected. increasing the loop bandwidth will result in a shorter pll lock time, but will allow more frequency components of jitter to be passed to the outputs. decreasing the loop bandwidth will decrease the output jitter, but will result in a longer pll lock time. 3.6.2.1 loop bandwidth of the video pll the capacitive component of the filter controlling the video loop bandwidth is determined by the video_cap_genlock register and the resistive component is determined by the video_res_genlock register. these two registers are located at addresses 26h and 27h, respectively, of the host interface. to determine the setting of video_res_genlock and video_cap_genlock, the following equations must be solved: where: bw = the desired video pll loop bandwidth jitterin = jitter present on applied hsync reference signal, in seconds h_feedback_divide = the numerator of the video pll divide ratio vi deo_r es_g enl ock 47 l og 2 6 bw jitterin h _f eedback_d i vi de () + = vi deo_c ap_g enl ock v i deo_r es_g enl ock 21 ?
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 49 of 102 h_feedback_divide represents the numerator of the ratio of the output clock frequency to the frequency of the h reference signal. for example, to program a loop bandwidth of 25hz given a 54mhz video clock and a reference with a 27mhz video clock and 1716 clocks per line, the following steps are necessary: 1. calculate h_feedback_divide: therefore, h_feedback_divide = 1716. 2. calculate the value for video_res_genlock: 3. calculate the value for video_cap_genlock: therefore, program video_res_genlock = 37 and video_cap_genlock = 16. note: the value programmed in the video_res_genlock register must be between 32 and 42. the value programmed in the video_cap_genlock register must be greater than 10. these limits define the exact range of loop bandwidth adjustment available. h _f eedback_d i vi de h_ref erence_d i vi de - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - f pclkout f hrefin - - - - - - - - - - - - - - - - - - - - - f pclkout 27 mhz = f hrefin 27 1716 - - - - - - - - - - - - mhz = h _f eedback_d i vi de h_ref erence_d i vi de - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -27 1716 27 - - - - - - - - - - - - 1716 1 - - - - - - - - - - - - = = vi deo_r es_g enl ock 47 l og 2 625 310 9 ? () 1716 () + 37 == vi deo_c ap_g enl ock 37 21 ? 16 ==
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 50 of 102 3.6.2.2 loop bandwidth of the audio pll (gs4901b only) the capacitive component of the filter controlling the audio loop bandwidth is determined by the audio_cap_genlock register and the resistive component is determined by the audio_res_genlock register. these two registers are located at addresses 39h and 3ah, respectively, of the host interface. to determine the setting of audio_res_genlock and audio_cap_genlock, the following equations must be solved: where: bw = the desired audio pll loop bandwidth jitterin = jitter present on output pclk, in seconds. a_feedback_divide = the numerator of the audio pll divide ratio a_feedback_divide is defined by the following equation: where f s is the fundamental audio sampling frequency and f out is the output video clock frequency. the integer constant, n, will depend on the fundamental audio sampling frequency as shown in table 3-5 . note: the value programmed in the audio_res_genlock register must be between 32 and 42. the value programmed in the audio_cap_genlock register must be greater than 10. these limits define the exact range of loop bandwidth adjustment available. table 3-5: integer constant value asr_sel[2:0]=100b enable_384fs = 0 value of constant (n) no x 3072 ye s ye s 1024 ye s no 153 6 note s : 1. enable_384fs corresponds to bit 5 of address 31h of the host interface. it is low by default. 2. x signifies dont care. this bit will be ignored when determining n. audio _r es_g enl ock 47 l og 2 6 bw jitterin a _feedback_d i vi de () + = audi o_c ap_g enl ock a udi o_r es_g enl ock 21 ? a _f eedback_d i vi de a _ref erence_d i vi de - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - n f s f out - - - - - - - - - - =
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 51 of 102 3.6.3 locking to digital timing from a deserializer as described in section 3.4.1 on page 41 , the gs4901b/GS4900B may be genlocked to either an analog reference, such as a black & burst signal, or to an sdi input via the digital h, v, and f blanking signals normally produced by a deserializer. when locking to an sdi input, the user should consider the possibility of a switch of the sdi signal upstream from the system. if the gs4901b/GS4900B is locked to the digital h, v, and f blanking signals produced by a deserializer, and the sdi input to the deserializer is switched such that the phase of the h input changes abruptly, the ref_lost output will remain low and the gs4901b/GS4900B will not crash lock to the new h phase. instead, the clock and timing outputs will very slowly drift towards the new phase. during this period of drift, the lock_lost output will be low, even though the device is not genlocked. the user should clear the run_window bits [2:0] of register adress 24h to force the device to crash lock should such a switch occur. this will cause the gs4901b/GS4900B to crash lock whenever it sees a disturbance of the input h signal. note: any action that causes an abrupt phase change of the h input to the gs4901b/GS4900B such that ref_lost is not triggered will cause the device to respond in the manner described above. in addition to the slow drifting behaviour outlined above, there may also be a random phase difference between the input vsync and output v sync signals occurring each time a switch in the sdi stream causes an abrupt phase change of the h input to the gs4901b/GS4900B. this will only occur when attempting to lock the 525-line sd output standards to the " f/1.001 " hd input reference standards. all line-based timing outputs are affected. the only way to ensure a constant phase difference between the input vsync signal and the line-based timing outputs is to reset the line-based counters after such a switch occurs. this is acheived by toggling bit 15 of register address 83h in the host interface. the device will then delay all line-based output timing signals by vsync lines relative to the input vsync reference, as described in note 3 of section 3.2.1.1 on page 36 . 3.7 clock synthesis the clock synthesis circuit generates the vide o clocks based on the vid_std[5:0] pins and host register settings. in the gs4901b, the clock synthesis circuit also generates the audio clock signals based on the asr_sel[2:0] pins and host register settings. the generated video and audio clocks may be further divided and are presented to the application layer via pins pclk1-pclk3 and aclk1-aclk3 respectively. 3.7.1 video clock synthesis the video clock generator is referenced to an internal crystal oscillator and is responsible for generating the pclk output signals.
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 52 of 102 the crystal oscillator requires an external 27mhz crystal connected to pins x1 and x2, or can be driven at lvttl levels from an external 27mhz source connected to x1. these two configurations are shown in figure 1-1 . four different video sample clock rates may be selected using the vid_std[5:0] pins of the device. section 1.4 on page 19 lists the video formats available using the vid_std[5:0] pins. if desired, the external vid_std[5:0] pins may be ignored by setting bit 1 of the video_control register, and the video standard may instead be selected via the vid_std[5:0] register of the host interface (see section 3.10.3 on page 67 ). although the external vid_std[5:0] pins will be ignored, they should not be left floating. once the video clock has been generated, it will be presented to the application layer via the pclk1 to pclk3 pins. by default, each of the 3 video clock outputs will produce the generated fundamental clock frequency. however, it is possible to select other rates for each pclk output by programming the pc lk_phase/divide registers beginning at address 2ch of the host interface (see section 3.10.3 on page 67 ). each pclk output may be individually programmed to provide one of the following: ? pclk fundamental frequency ? fundamental frequency /2 ? fundamental frequency /4 when all six vid_std[5:0] pins are set low, the video clocks will be disabled. pclk1 and pclk2 will go low and pclk3/pclk3 will be high impedance. note: if the pclk divider bits of registers 2ch - 2eh are set to enable a divide by 2 or divide by 4, the resultant divided clock will align with the falling edge of the output h sync timing signal either on its rising or falling edge.
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 53 of 102 the pclk1 to pclk3 outputs may also be individually delayed with respect to the eight timing_out signals to allow for skew control downstream from the gs4901b/GS4900B. using the pclk_phase/divide registers, the phase of each clock may be delayed up to a nominal 10.3ns in 16 steps of approximately 700ps each ( table 3-6 ). this delay is available in addition to the genlock timing offset phase adjustment described in section 3.2.1 on page 35 . additionally, the current drive capability of pclk1 and pclk2 may be set high or low using the pclk_phase/divide registers. by default the current drive will be low. 3.7.2 audio clock synthesis (gs4901b only) the audio clock generator is referenced to the internal pclk signal and is responsible for generating the aclk output signals. three audio clock output pins, aclk1 to aclk3, are available to the application layer. the fundamental sampling frequency, fs, is selected using the asr_sel[2:0] pins as shown in table 3-7 . if desired, the external asr_sel[2:0] pins may be ignored by setting bit 2 of the audio_control register and the sampling frequency may instead be programmed in the asr_sel[2:0] register of the host interface (see section 3.10.3 on page 67 ). although the external asr_sel[2:0] pins will be ignored, they should not be left floating. table 3-6: video clock phase adjustment host settings p c lkn_phase[3:0] s ettin g 0 h 1h 2h 3h 4h 5h 6 h7h8h9hahbh c hdheh fh phase in c rement (ns) 0 0.7 1.4 2.1 2.8 3.5 4.2 4.9 5. 66 .3 7.0 7.7 8.4 9.1 9.8 10.3 note s : 1. the phase increments listed above are nominal values. 2. the phase of pclk is delayed relative to the timing_out pins.
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 54 of 102 when all three asr_sel[2:0] pins are set low, the audio clock outputs will be high impedance. in this case, the application layer may continue to power the aud_pll_vdd pin; however, to minimize noise and power consumption, aud_pll_vdd may be grounded. by default, after system reset, aclk1 to aclk3 will output clock signals at 256fs, 64fs, and fs respectively. different division ratios for each output pin may be selected by programming the aclk_fs_multiple registers beginning at address 3fh of the host interface (see section 3.10.3 on page 67 ). the encoding of this register is shown in table 3-8 . clock outputs of 512fs, 348fs, 256fs, 192fs, 128fs, 64fs, fs, and z bit are selectable on a pin by pin basis. the z bit will go high for one fs period every 192 fs periods. its phase is not defined by any timing event in the gs4901b, and so is arbitrary. table 3-7: audio sample rate select asr_sel[2:0] sampling frequency (khz) 000 au d io c lo c k g eneration disa b le d 001 32 010 44.1 011 48 100 9 6 101 s low 32* 110 s low 44.1* 111 s low 48* * s low 32, 44.1, an d 48 are availa b le only when the vi d eo stan d ar d sele c te d is 23.98, 29.97, or 59.94 frame rate b ase d . they refer to 32khz, 44.1khz, or 48khz multiplie d b y 1000/1001 to maintain the 1, 2, or 3 frame sequen c e normally asso c iate d with 24, 30, an d 6 0 fps vi d eo. table 3-8: audio clock divider aclkn_fs_multiple[3:0] audio clock frequency 000 fs 001 6 4fs 010 128fs 011 192fs* 100 25 6 fs 101 384fs* 110 512fs**
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 55 of 102 the fs signal on aclk1-3 has an accurate 50% duty cycle, and can be used for left/right definition, with the following exception: if fs = 96khz and the user configures the host interface such that one of the three aclk pins is set to output a clock signal at 192fs or 384fs, the 512fs clock will have a 33% duty cycle. all audio clocks are initially reset on the rising edge of the afs pulse, ensuring that video to audio clock synchronization is correct. during normal operation, the audio clock edge is allowed to drift slightly with respect to the afs pulse. by default, the audio clock will be reset directly by the afs pulse if it drifts more than approximately +/-0.1us from the rising edge of the afs pulse. however, after device reset, or after the application of a new input reference, the aclk outputs may sometimes be offset from the afs pulse by up to several microseconds. the offset will remain until the device is reset or the reference removed and re-applied. the user may avoid this offset by minimizing the width of the afs_reset_window using bits 9-7 of register 31h for the duration of the audio pll locking process. once the audio pll is locked, bit 1 of register 1fh will be set high, and the afs_reset_window may be set as desired. see table 3-9 . 3.7.2.1 audio to video clock phasing the important aspect of the audio to video phase relates to the way in which the afs pulse is used to reset the audio clock dividers so as to line up the leading edge of the audio clocks with the leading edge of the h sync pulse on line 1 of the first field in the audio frame sequence. the afs pulse is further discussed in section 3.8.2 on page 59 . 111 z- b it *this settin g is only availa b le when the ena b le_384fs b it of the au d io_ c ontrol re g ister is hi g h. **512fs c lo c k will have a 33% d uty c y c le when the ena b le_384fs b it is hi g h an d fs = 9 6 khz. table 3-8: audio clock divider (continued) aclkn_fs_multiple[3:0] audio clock frequency table 3-9: encoding scheme for afs_reset_window window tolerance (us) af s _reset_win d ow (a dd ress 31h) fs = 32khz fs = 44.1khz fs = 48 khz fs = 9 6 khz (ena b le_384fs = 1) fs = 9 6 khz (ena b le_384fs = 0) 000 0.044 0.033 0.030 0.030 0.044 001 0.084 0.0 6 2 0.057 0.057 0.084 010 ( d efault) 0.1 66 0.121 0.112 0.112 0.1 66 011 0.329 0.239 0.220 0.220 0.329 1xx 0. 6 54 0.475 0.437 0.437 0. 6 54 note: ?x? si g nifies ? d on?t c are.? the b it settin g will b e i g nore d .
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 56 of 102 625i 50 format for the 48khz sampling rate, the audio to video phase relationship for 625/50i reference signals is provided by the device in accordance with the ebu recommended practice r83-1996. the start of an audio frame (fs clock) will align with the 50% point of the h sync input of line 1 of each video frame (+/- the allowable drift specified in table 3-9 ). 525i 59.94 format for 525/59.94 ntsc reference signals, the device will observe the 5-frame phase-relationship inherent with this video standard, aligning the audio clocks with the 50% point of the h sync input of line 1 on every fifth frame (+/- the allowable drift specified in table 3-9 ). the number of audio sample clocks during a video frame is shown in table 3-10 for 32, 44.1, and 48khz audio sampling frequencies. the external 10fid input pin may be used to resynchronize other audio clock frequencies, according to table 3-10 , by applying an active signal during the reference hsync of line 1 of the appropriate video frame. please see section 3.4.2 on page 42 for more details on the 10fid input pin. in the case where 10fid is not present as a reference signal, the gs4901b will automatically generate an afs pulse appropriate to the format selected, and use it to create an audio frame sequence. host interface control of afs and 10fid alternatively, the user may program the device via the host interface to re-time the audio frame sequence and 10 field-id. using register 1ah, a pulse may be generated to reset the afs and/or 10fid dividers at the start of an output video frame (see section 3.10.3 on page 67 ). if using the host interface to reset the afs pulse, the device may be configured to ignore the input 10fid reference pin. to disable the signal on the external 10fid pin from resetting the afs output pulse, set bit 0 of the audio_control register high. if using the host interface to reset the 10fid pulse, the external 10fid pin must be grounded. table 3-10: audio sampling frequency to video frame rate synchronization audio samples per video frame au d io s ample rate (khz) 24fps 25fps 29.97fps 30fps 50fps 59.94fps 6 0fps 32 4000/3 1280 1 6 01 6 /15 3200/3 6 40 8008/15 1 6 00/3 44.1 3 6 75/2 17 6 4 147147/100 1470 882 147147/200 735 48 2000 1920 8008/5 1 6 00 9 6 0 4004/5 800 * fps = frames per se c on d .
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 57 of 102 3.8 video timing generator the internal pclk signal generated by the clock synthesis circuit is used to produce horizontal, vertical, and frame based timing output signals. the signals generated and available to the application layer via the timing_out pins are: h sync, h blanking, v sync, v blanking, f sync, f digital, de, 10fid, afs (gs4901b only), and user_1~4. these signals are defined in section 1.5 on page 23 . additional information pertaining to the 10fid, afs, and user_1~4 signals can be found in the sub-sections below. when the gs4901b/GS4900B is operating in genlock mode, the h, v, and f based output timing signals are synchronized to the h, v, and f reference signals applied to the inputs by the application layer. the video timing outputs may be offset from the input reference by programming the genlock offset registers beginning at address 1bh of the host interface (see section 3.2.1.1 on page 36 ). all timing_out signals have selectable polari ty. the default polarities for each signal are given in the descriptions in section 1.5 on page 23 . 3.8.1 10 field id pulse as described in table 1-3 , the 10 field id (10fid) output signal is used in the identification of film to video cadence. it is only generated for 29.97, 30, 59.94, and 60fps formats. the 10fid pulse is generated on every 5 th frame for 29.97 and 30fps formats, and every 10 th frame on 59.94 and 60fps formats. by default, the 10fid signal is set high on the leading edge of the h sync output for the duration of line 1 of field 1 at the start of the 10 field sequence. this is shown in figure 3-6 . alternatively, by setting bit 4 of the video_control register at address 4ch of the host interface, the 10fid output signal may be configured to go high (default polarity) on the leading edge of the h sync pulse of line 1 of the first field in the 10 field sequence, and be reset low on the leading edge of the h sync pulse of line 1 of the second field in the 10 field sequence. this is shown in figure 3-7 . fi g ure 3- 6 : default 10fid output timin g 10fid output horizontal sync output total line line 1, frame 1 every 'n' frames line 1 every n frames where: n = 5 @ 29.97 fps, 30 fps n = 10 @ 59.94 fps, 60 fps
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 58 of 102 fi g ure 3-7: optional 10fid output timin g the phasing of the divide by n frame counter may be reset by an external pulse on the 10fid input pin, or via register 1ah of the host interface (see section 3.10.3 on page 67 ). note: if a 10fid input signal is not provided to the device, the 10fid output signal will be invalid until the user initiates a reset via the host interface. the user should also reset the 10fid signal via the host if at any time the h input reference signal is removed and then re-applied. 3.8.2 audio frame synchronizing pulse (gs4901b only) as described in table 1-3 , the audio frame synchronizing (afs) pulse identifies the frame, within an n frame sequence, in which the audio sample rate clock is aligned with the h sync of line 1. it is generated for all video formats. the leading edge of the afs output pulse is co-timed with the h sync corresponding to line 1 of every n th frame in the sequence, and therefore identifies the exact time at which the audio sample rate clock and video pclk have synchronous leading edges. the number of frames in the sequence, n, is determined by the video frame rate and the audio clock frequency. these are selected using the vid_std[5:0] and asr_sel[2:0] pins or via the host interface. by default, the afs pulse is 1 line long, as shown in figure 3-8 . alternatively, by setting bit 1 of the audio_control register, the afs output signal may be configured to go high on the leading edge of the h sync pulse of line 1 of the first field in the ?n? frame sequence, and be reset low on the leading edge of the h sync pulse of line 1 of the second field in the sequence. the afs timing in this configuration is similar to the 10fid optional timing shown in figure 3-7 . 10fid output horizontal sync output total field line 1 every n frames where: n = 5 @ 29.97 fps, 30 fps n = 10 @ 59.94 fps, 60 fps
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 59 of 102 fi g ure 3-8: af s output timin g the phasing of the divide by n counter can be controlled by the 10fid input or via designated registers in the host interface. by default, the 10fid input pin controls the afs phase (in addition to controlling the 10fid phase); however, this feature may be disabled by setting bit 0 of the audio_control register (see section 3.10.3 on page 67 ). in addition, the afs signal may be reset via register 1ah. 3.8.3 user_1~4 as described in table 1-3 , the gs4901b/GS4900B offers 4 user programmable output signals which are available independent of the selected output video format. each user signal is individually programmable and the polarity, position, and width of each output may be defined with respect to the digital output timing of the device. each output signal may be programmed in both the horizontal and vertical dimensions relative to the leading edges of h blanking and v blanking. if desired, the pulses produced may then be combined with a logical and, or, or xor function to produce a composite signal (for example, a horizontal back porch pulse during active lines only, or the active part of lines 15 through 20 for vertical information retrieval). by default, the and, or, and xor functions are disabled. therefore, when a user signal is selected using the output_select registers of the host interface, the signal will go low (default polarity) at the h_start pixel and return high after the h_stop pixel. setting the and bit high, for example, will cause the user signal to be active only when user_h is active and user_v is active (i.e. the pixel is between both h_start and h_stop and v_start and v_stop). see figure 3-9 . note: the effective horizontal range of the four user-defined timing signals is [h_start + 1, h_stop], except when h_start = 1, in which case the range is [h_start, h_stop]. this prevents the user from specifying an output user signal that begins on pixel 2 of a line. in the case of interlaced output formats, the programmed vertical start and stop lines refer to the start and stop lines of the generated user signal on the odd fields. the start afs_out horizontal sync output total line line 1 every n frames where: n = 1 @ 25fps: fs = 32khz n = 1 @ 25fps, 30fps & 60fps: fs = 44.1khz n = 1 @ 25fps, 30fps & 60fps; fs = 48khz n = 2 @ 24fps; fs = 44.1khz, 48khz n = 3 @ 24fps, 30fps & 60fps: fs = 32khz n = 5 @ 29.97fps & 59.94fps; fs = 48khz n = 15 @ 29.97fps & 59.94fps; fs = 32khz n = 100 @ 29.97fps; fs = 44.1khz n = 200 @ 59.94fps; fs = 44.1khz
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 60 of 102 and stop lines of the user signal on the even fields will be v_start - 1 and v_stop - 1, respectively. for example, if vid_std[5:0] = 3, the odd fields will have 263 lines and the even fields will have 262 lines. a user-defined vertical pulse programmed to start on line 12 and stop on line 17 will start on frame lines 12 and 274, and stop on frame lines 17 and 279. the designated registers for programming each user signal are located in the host interface beginning at address 57h. see section 3.10.3 on page 67 . fi g ure 3-9: u s er pro g ramma b le output s i g nal and=0, or=0, xor=0 (default) and=0, or=1 shading indicates when user_x signal is active h_start h_stop v_start v_stop and=1 h_start h_stop v_start v_stop h_start h_stop v_start v_stop and=0, or=0, xor=1 h_start h_stop v_start v_stop
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 61 of 102 3.8.4 timing_out pins the horizontal, vertical, and frame based timing output signals for the selected video format are available to the application layer via the timing_out_1 to timing_out_8 pins. programmable crosspoint switch each timing_out pin outputs a default signal as shown in table 1-3 . alternatively, a crosspoint switch may be programmed via the eight output_select registers of the host interface, allowing the user to select wh ich output signal is directed to each timing_out pin (see section 3.10.3 on page 67 ). any signal may be sent to more than one pin if desired. table 3-11 outlines the encoding scheme of the eight output_select registers, which begin at address 43h of the host interface. table 3-11: crosspoint select output_select_n bit settings output signal 0000 hi g h impe d an c e 0001 h s yn c 0010 h blankin g 0011 v s yn c 0100 v blankin g 0101 f s yn c 0110 f di g ital 0111 10fid 1000 de 1001 reserve d 1010 af s * 1011 u s er_1 1100 u s er_2 1101 u s er_3 1110 u s er_4 1111 reserve d *af s is only availa b le on the gs 4901b. the b it settin g 1010 b will b e i g nore d b y the gs 4900b.
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 62 of 102 3.8.4.1 selectable current drive and polarity the current-drive of each timing output pin is also selectable via the output_select registers. the current drive of each timing_out pin is low by default. however, it may be set high to accommodate certain applications. additionally, the polarity register of the host interface may be programmed to select the polarity of each timing output signal. 3.9 extended audio mode for hd demux using the gennum audio core the gs4901b/GS4900B has been designed to interface with gennum's fpga audio core in order to provide a 24.576mhz clock (512 * 48khz) locked to the audio clock contained in the embedded audio data packets of an hd-sdi stream. it is the responsibility of the user to divide this clock by 4 to obtain the 6.144mhz required by the core. in hd demux mode, the fpga audio core will extract an audio clock from the embedded audio data packets and present a 24khz clock to the gs4901b/GS4900B via the aclkdiv2a (for group a) and aclkdiv2b (for group b) outputs. the embedded clock must be 48khz. the 24khz reference signals for each audio group must be applied to the hsync input pin of a gs4901b/GS4900B, while a divided version of this signal must be applied to the vsync input pin. the divided signal must meet the requirements for vsync validity given in section 3.5.2 on page 44 . it is recommended that the vsync signal be generated by dividing the 24khz reference applied to hsync by 512 to give 46.875hz. to enable the extended audio mode, the user must do the following: 1. set vid_std[5:0] = 4d. 2. set the f_lock_mask and v_lock_mask bits [4:3] of register address 16h to 1. 3. set the ext_audio_mode register address 81h to 20c1h. 4. toggle bit [6] of register address 16h. in this mode, the gs4901b/GS4900B will produce a 24.576mhz clock on its pclk output pins that is locked to the 24khz extracted audio clock reference applied to hsync. it will not lock to any other reference frequency. the user may then divide this frequency by 4 using the programmable dividers in the gs4901b/GS4900B.
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 63 of 102 fi g ure 3-10: au d io c lo c k blo c k dia g ram for hd demux operation 3.10 gspi host interface the gspi, or gennum serial peripheral interface, is a 4-wire interface provided to allow the host to enable additional features of the gs4901b/GS4900B and/or to provide additional status information through configuration registers in the device. the gspi comprises a serial data input signal , sdin, a serial data output signal, sdout, an active low chip select, cs , and a burst clock, sclk. the burst clock must have a duty cycle between 40% and 60%. because these pins are shared with the jtag interface port, an additional control signal pin, jtag/host is provided. when jtag/host is low, the gspi interface is enabled. when operating in gspi mode, the sclk, sdin, and cs signals are provided by the application interface. the sdout pin is a non-clocked loop-through of sdin and may be connected to the sdin pin of another device, allowing multiple devices to be connected to the gspi chain. the interface is illustrated in figure 3-11 . fp g a aout1_2 aout3_4 aout5_ 6 aout7_8 s erial vi d eo input hd audio demux c ore p c lk gs 49xxb vi d eo data w c lka gs 1559 deserializer a c lk 6 4a w c lk b p c lk1 a c lk128 b a c lk 6 4 b vin[19:0] p c lk a c lk d iv2 b p c lk1 gs 49xxb a c lk128a a c lk d iv2a /512 /512
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 64 of 102 fi g ure 3-11: gs pi appli c ation interfa c e c onne c tion all read or write access to the gs4901b/GS4900B is initiated and terminated by the host processor. each access always begins with a 16-bit command word on sdin indicating the address of the register of interest. this is followed by a 16-bit data word on sdin in write mode, or a 16-bit data word on sdout in read mode. application host sclk sclk sclk cs1 sdout sdin sdout sdout cs sdin sdin cs2 gs4911b/gs4910b cs gs4911b/gs4910b
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 65 of 102 3.10.1 command word description the command word consists of 16 bits transmitted msb first and includes a read/write bit, an auto-increment bit and a 12-bit address. figure 3-12 shows the command word format and bit configurations. command words are clocked into the gs4901b/GS4900B on the rising edge of the serial clock, sclk, which operates in a burst fashion. when the auto-increment bit is set low, each command word must be followed by only one data word to ensure proper operation. if the auto-increment bit is set high, the following data word will be written into the address specified in the command word, and subsequent data words will be written into incremental addresses. this facilitates multiple address writes without sending a command word for each data word. auto-increment may be used for both read and write access. fi g ure 3-12: c omman d wor d format fi g ure 3-13: data wor d format 3.10.2 data read and write timing read and write mode timing for the gspi interface is shown in figure 3-14 and figure 3-15 respectively. the timing parameters are defined in table 3-12 . when several devices are connected to the gspi chain, only one cs should be asserted during a read sequence. during the write sequence, all command and following data words input at the sdin pin are output at the sdout pin as is. where several devices are connected to the gspi chain, data can be written simultaneously to all the devices that have cs set low. msb lsb a4 a5 a6 a8 a7 a9 a3 a2 a1 a0 a10 a11 autoinc rsv rsv r/w rsv = reserved. must be set to zero. r/w: read command when r/w = 1 write command when r/w = 0 msb lsb d4 d5 d6 d8 d7 d9 d3 d2 d1 d0 d10 d11 d12 d13 d14 d15 table 3-12: gspi timing parameters parameter definition specification t 0 the minimum d uration of time c hip sele c t, cs , must b e low b efore the first sc lk risin g e dg e. 1.5 ns t 1 the minimum sc lk perio d . 100 ns
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 66 of 102 fi g ure 3-14: gs pi rea d mo d e timin g fi g ure 3-15: gs pi write mo d e timin g 3.10.3 configuration and status registers table 3-13 summarizes the gs4901b/GS4900B's internal status and configuration registers. all registers are available to the host via the gspi and are all individually addressable. t 2 duty c y c le tolerate d b y sc lk. 40% to 6 0% t 3 minimum input setup time. 1.5 ns t 4 the minimum d uration of time b etween the last sc lk c omman d wor d (or d ata wor d if the auto-in c rement b it is hi g h) an d the first sc lk of the d ata wor d (write c y c le). 37.1 ns t 5 the minimum d uration of time b etween the last sc lk c omman d wor d (or d ata wor d if the auto-in c rement b it is hi g h) an d the first sc lk of the d ata wor d (rea d c y c le). 148.4 ns t 6 minimum output hol d time (15pf loa d ). 1.5 ns t 7 the minimum d uration of time b etween the last sc lk of the gs pi transa c tion an d when cs c an b e set hi g h. 37.1 ns t 8 minimum input hol d time. 1.5 ns table 3-12: gspi timing parameters (continued) parameter definition specification sclk cs sdin sdout t 5 t 6 r/w rsv rsv autoinc a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 r/w rsv rsv autoinc a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 t 3 sclk cs sdin sdout t 0 t 1 t 2 t 4 r/w rsv rsv autoinc a11 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a10 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 r/w rsv rsv autoinc a11 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a10 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 t 7 t 8
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 67 of 102 table 3-13: configuration and status registers register name address bit description r/w default r s vd 00h - 09h ? reserve d .?? h_perio d 0ah 15-0 c ontains the num b er of 27mhz pulses in the input h s yn c perio d . this re g ister is set b y the referen c e format dete c tor b lo c k usin g the h s yn c si g nal present on the external h s yn c input pin. note: if the referen c e is remove d this re g ister will remain un c han g e d until a new referen c e with a d ifferent h s yn c perio d is applie d . referen c e: s e c tion 3.5.1 on pa g e 43 rn/a h_1 6 _perio d 0bh 15-0 c ontains the num b er of 27mhz pulses in 1 6 h s yn c perio d s. this re g ister is set b y the referen c e format dete c tor b lo c k usin g the h s yn c si g nal present on the external h s yn c input pin. it is useful for 1/1.001 d ata d ete c tion. note: if the referen c e is remove d this re g ister will remain un c han g e d until a new referen c e with a d ifferent h s yn c perio d is applie d . referen c e: s e c tion 3.5.1 on pa g e 43 rn/a v_lines 0 c h 15-0 c ontains the num b er of h s yn c perio d s in the input v s yn c interval. this re g ister is set b y the referen c e format dete c tor b lo c k usin g the si g nals present on the external h s yn c an d v s yn c input pins. note: if the referen c e is remove d this re g ister will remain un c han g e d until a new referen c e with a d ifferent v s yn c perio d is applie d . referen c e: s e c tion 3.5.1 on pa g e 43 rn/a v_2_lines 0dh 15-0 c ontains the num b er of h s yn c perio d s in 2 v s yn c intervals. this re g ister is set b y the referen c e format dete c tor b lo c k usin g the si g nals present on the external h s yn c an d v s yn c input pins. note: if the referen c e is remove d this re g ister will remain un c han g e d until a new referen c e with a d ifferent v s yn c perio d is applie d . referen c e: s e c tion 3.5.1 on pa g e 43 rn/a f_lines 0eh 15-0 c ontains the num b er of h s yn c perio d s in the input f s yn c interval. this re g ister is set b y the referen c e format dete c tor b lo c k usin g the si g nals present on the external h s yn c an d f s yn c input pins. note: if the referen c e is remove d this re g ister will remain un c han g e d until a new referen c e is applie d . if the new referen c e d oes not in c lu d e an f s yn c pulse, this re g ister will b e set to zero. referen c e: s e c tion 3.5.1 on pa g e 43 rn/a
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 68 of 102 input_ s tan d ar d 0fh 15-13 reserve d . s et these b its to zero when writin g to 0fh. ?? 0fh 12 for c e_input - s et this b it hi g h to for c e the gs 4901b/ gs 4900b to re c o g nize the applie d input referen c e format as the stan d ar d pro g ramme d in b its 11- 6 of this re g ister. r/w 0 0fh 11- 6 for c e d _ s tan d ar d - when b it 12 is set hi g h, the gs 4901b/ gs 4900b will use the value pro g ramme d in these b its, rather than the value in b its 5-0, to d etermine the input referen c e format. the 6 - b it value pro g ramme d here shoul d always c orrespon d to the vid_ s td[5:0] value of the applie d referen c e. these b its shoul d not b e pro g ramme d for normal operation. r/w 0 0fh 5-0 dete c te d _ s tan d ar d - c ontains the vi d eo stan d ar d applie d to the input referen c e pins on c e it has b een d ete c te d . these b its are set b y the referen c e format dete c tor b lo c k an d c orrespon d to the vid_ s td[5:0] value of the stan d ar d as liste d in ta b le 1-2 . the dete c te d _ s tan d ar d b its will b e set to zero if no input referen c e si g nal is applie d or if the input referen c e si g nal is not an automati c ally re c o g nize d vi d eo format. otherwise the value will b e b etween 1 an d 54. referen c e: s e c tion 3.5.2 on pa g e 44 r/w n/a am b _ s t d _ s el 10h 15-11 reserve d . s et these b its to zero when writin g to 10h. ?? 10h 10-0 the user may set this re g ister to d istin g uish b etween d ifferent formats that look i d enti c al to the internal referen c e format dete c tor b lo c k. s ee ta b le 3-2 . referen c e: s e c tion 3.5.2.1 on pa g e 44 r/w 0 table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 69 of 102 referen c e_ s tan d ar d _disa b le 13h-11h 38-0 the referen c e_ s tan d ar d _disa b le re g ister may b e use d to d isa b le/ena b le one or more of the input stan d ar d s g iven in ta b le 1-2 from b ein g re c o g nize d b y the d evi c e an d use d to g enlo c k the output. this is d one b y settin g the b it hi g h that c orrespon d s to the vid_ s td[5:0] value of the vi d eo format. for example, if b it 5 is set hi g h, then the output c lo c k an d timin g si g nals will not g enlo c k to an input referen c e with timin g c orrespon d in g to vid_ s td[5:0] = 5 in ta b le 1-2 . likewise, to ena b le re c o g nition of vid_ s td[5:0] = 2 6 (1080i/59.94) as an input referen c e format, the user must set b it 2 6 low. a dd ress 13h = b its 38-32* a dd ress 12h = b its 31-1 6 a dd ress 11h = b its 15-0 *bits 47-39 of a dd ress 13h shoul d always b e written hi g h. referen c e: s e c tion 3.5 on pa g e 43 r/w ffffh ffffh f800h r s vd 14h ? reserve d ?? table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 70 of 102 g enlo c k_ s tatus 15h 15- 6 reserve d .?? 15h 5 referen c e_lo c k - this b it will b e hi g h when the output is su cc essfully g enlo c ke d to the input (i.e. when b its 4-1 of this re g ister are hi g h an d are not maske d b y b its 4-2 of re g ister 1 6 h). the lo c k_lo s t output pin is an inverte d c opy of this b it. referen c e: s e c tion 3. 6 .1 on pa g e 49 rn/a 15h 4 f_lo c k - this b it will b e hi g h when the output f is su cc essfully g enlo c ke d to the f s yn c input. note: if the input referen c e d oes not in c lu d e an f s yn c input, this b it will have the same settin g as v_lo c k ( b it 3). referen c e: s e c tion 3. 6 .1 on pa g e 49 rn/a 15h 3 v_lo c k - this b it will b e hi g h when the output v is su cc essfully g enlo c ke d to the v s yn c input. referen c e: s e c tion 3. 6 .1 on pa g e 49 rn/a 15h 2 h_lo c k - this b it will b e hi g h when the output h is su cc essfully g enlo c ke d to the h s yn c input. referen c e: s e c tion 3. 6 .1 on pa g e 49 rn/a 15h 1 c lo c k_lo c k - this b it will b e hi g h when the vi d eo c lo c k is lo c ke d to the internal v_pll and the au d io c lo c k is lo c ke d to the internal a_pll (i.e. b its 0 an d 1 of re g ister 1fh are hi g h). referen c e: s e c tion 3. 6 .1 on pa g e 49 rn/a 15h 0 referen c e_present - this b it will b e hi g h when a vali d input referen c e si g nal has b een applie d to the d evi c e. the ref_lo s t output pin is an inverte d c opy of this b it. referen c e: s e c tion 3.5.2 on pa g e 44 rn/a table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 71 of 102 g enlo c k_ c ontrol 1 6 h 15-7 reserve d . s et these b its to zero when writin g to 1 6 h. ?? 1 6 h 6 this b it is use d to ena b le the exten d e d au d io mo d e of the d evi c e. r/w 0 1 6 h5 g enlo c k_from_host - set this b it hi g h to ena b le vi d eo g enlo c k c ontrol via the host interfa c e instea d of the external g enlo c k pin (see b it 0 of this re g ister). referen c e: s e c tion 3.2 on pa g e 35 r/w 0 1 6 h 4 f_lo c k_mask - if this b it is set hi g h, the gs 4901b/ gs 4900b will i g nore the status of f_lo c k ( b it 4 of re g ister 15h) when d eterminin g the status of referen c e_lo c k ( b it 5 of re g ister 15h). referen c e: s e c tion 3. 6 .1 on pa g e 49 r/w 0 1 6 h 3 v_lo c k_mask - if this b it is set hi g h, the gs 4901b/ gs 4900b will i g nore the status of v_lo c k ( b it 3 of re g ister 15h) when d eterminin g the status of referen c e_lo c k ( b it 5 of re g ister 15h). referen c e: s e c tion 3. 6 .1 on pa g e 49 r/w 0 1 6 h2h_lo c k_mask - if this b it is set hi g h, the gs 4901b/ gs 4900b will i g nore the status of h_lo c k ( b it 2 of re g ister 15h) when d eterminin g the status of referen c e_lo c k ( b it 5 of re g ister 15h). referen c e: s e c tion 3. 6 .1 on pa g e 49 r/w 0 1 6 h1drift_ c rash - when this b it is set hi g h, the g enerate d vi d eo c lo c k will d rift lo c k to a new input referen c e rather than c rash lo c k. referen c e: s e c tion 3. 6 .1 on pa g e 49 r/w 0 1 6 h0 g enlo c k - this b it may b e use d instea d of the external pin to g enlo c k the output vi d eo format to the input referen c e. this b it will b e i g nore d if b it 5 of this re g ister is low. referen c e: s e c tion 3.2 on pa g e 35 r/w 0 r s vd 17h-19h ? reserve d ?? table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 72 of 102 10fid_af s _reset 1ah 15-4 reserve d . s et these b its to zero when writin g to 1ah. ?? 1ah 3 af s _reset ( gs 4901b only) - set this b it hi g h to use reset_ s yn c ( b it 0 of re g ister 1ah) to reset the output af s pulse. note: this b it will remain low in the gs 4900b. s et this b it low when writin g to a dd ress 1ah of the gs 4900b. referen c e: s e c tion 3.7.2.1 on pa g e 5 6 r/w 0 1ah 2 10fid_reset - set this b it hi g h to use reset_ s yn c ( b it 0 of re g ister 1ah) to reset the output 10fid pulse. note: if a 10fid input si g nal is not provi d e d to the d evi c e, the user must g enerate a reset usin g this b it to initiate the 10fid timin g output. in this c ase, the 10fid input pin must b e g roun d e d . referen c e: s e c tion 3.7.2.1 on pa g e 5 6 r/w 0 1ah 1 reserve d . s et this b it to zero when writin g to 1ah. ? ? 1ah 0 reset_ s yn c - resets the pulses d es c ri b e d in b its 2, an d 3 a b ove. the reset pulse is g enerate d if this b it is pulse d (low to hi g h to low) d urin g the output frame imme d iately prior to the frame the reset is to o cc ur. this reset will operate in d epen d ently of any other resets, for example from the referen c e input. r/w 0 h_offset 1bh 15-0 the output h si g nal may b e d elaye d with respe c t to the input referen c e b y the num b er of pixels pro g ramme d in this re g ister. ( s ee s e c tion 3.2.1.1 on pa g e 3 6 ). the value pro g ramme d in this re g ister shoul d not ex c ee d the maximum num b er of c lo c k perio d s per line of the out g oin g stan d ar d . horizontal a d van c es may b e a c hieve d b y pro g rammin g a value equal to the maximum allowa b le offset minus the d esire d a d van c e. note: this re g ister is internally rea d b y the d evi c e on c e per fiel d . at that time any new value pro g ramme d is sent to the internal offset c ir c uitry. referen c e: s e c tion 3.2.1.1 on pa g e 3 6 r/w 0 table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 73 of 102 v_offset 1 c h 15-0 the output v si g nal may b e d elaye d with respe c t to the input referen c e b y the num b er of lines pro g ramme d in this re g ister. ( s ee s e c tion 3.2.1.1 on pa g e 3 6 ). the value pro g ramme d in this re g ister shoul d not ex c ee d the maximum num b er of lines per frame of the out g oin g stan d ar d . verti c al a d van c es may b e a c hieve d b y pro g rammin g a value equal to the maximum allowa b le offset minus the d esire d a d van c e. note: this re g ister is internally rea d b y the d evi c e on c e per fiel d . at that time any new value pro g ramme d is sent to the internal offset c ir c uitry. referen c e: s e c tion 3.2.1.1 on pa g e 3 6 r/w 0 c lo c k_phase_offset 1dh 15-0 phase_offset - the output c lo c k an d d ata phase may b e offset with respe c t to the input referen c e b y the num b er of in c rements pro g ramme d in this re g ister. the in c rement step size d epen d s on the vi d eo c lo c k frequen c y. the en c o d in g s c heme for this re g ister is shown in ta b le 3-1 . note: this re g ister must b e c leare d to a c hieve a c lo c k phase offset of zero. referen c e: s e c tion 3.2.1.1 on pa g e 3 6 r/w 0 max_ref_delta 1eh 15-0 the value pro g ramme d in this re g ister c ontrols the allowe d d evian c e from the expe c te d frequen c y on the referen c e h s yn c b efore the internal vi d eo pll loses lo c k. the en c o d in g s c heme is shown in ta b le 3-3 . referen c e: s e c tion 3.5.4 on pa g e 47 r/w 000bh table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 74 of 102 vi d eo_ s tatus 1fh 15-5 reserve d .?? 1fh 4 ref_h_polarity - status re g ister to in d i c ate the d ete c te d h s yn c polarity ( ' 1 ' for positive, ' 0 ' for ne g ative). this b it will b e zero when no referen c e si g nal is present. referen c e: s e c tion 3.4.3 on pa g e 42 rn/a 1fh 3 ref_v_polarity - status re g ister to in d i c ate the d ete c te d v s yn c polarity ( ' 1 ' for positive, ' 0 ' for ne g ative). this b it will b e zero when no referen c e si g nal is present an d for d i g ital b lankin g input referen c es. referen c e: s e c tion 3.4.3 on pa g e 42 rn/a 1fh 2 ref_blank_timin g - status re g ister to in d i c ate the input d ete c tion of h b lankin g vs. h syn c timin g (?1? for b lankin g , ' 0 ' for syn c timin g ). this b it will b e zero when no referen c e si g nal is present. referen c e: s e c tion 3.4.3 on pa g e 42 rn/a 1fh 1 a_pll_lo c k ( gs 4901b only)- this b it will b e hi g h when the g enerate d au d io c lo c k is lo c ke d to the vi d eo c lo c k referen c e. note: this b it will remain hi g h in the gs 4900b. referen c e: b it 1 of re g ister 15h. rn/a 1fh 0 v_pll_lo c k - this b it will b e hi g h when the g enerate d vi d eo c lo c k is lo c ke d to the h s yn c input referen c e. referen c e: b it 1 of re g ister 15h. rn/a r s vd 20h-23h ? reserve d ?? table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 75 of 102 c onst c f_ g enlo c k 24h 15-8 c rash_time - c ontrols the c rash lo c k perio d of vi d eo pll lo c kin g pro c ess. this time c ontri b utes to the total pll lo c k time g iven in the a c c hara c teristi c s ta b le. the time of the c rash pro c ess in h referen c e perio d s is d etermine d b y [ c rash_time x 4] + 1. the d efault value of these b its will vary d epen d in g on the output vi d eo stan d ar d sele c te d . referen c e: s e c tion 3. 6 .1 on pa g e 49 r/w ? 24h 7-3 lo c k_lost_threshol d - c ontrols the threshol d of the lo c k in d i c ation c ir c uit. a lar g er value pro g ramme d in this re g ister c an in c rease the sta b ility of the lo c k_lo s t output si g nal when the input h referen c e si g nal is su b je c t to lar g e amounts of low frequen c y jitter. a lar g er value in this re g ister will also in c rease the lo c k in d i c ation time, althou g h not the a c tual lo c k time of the d evi c e. the d efault value of these b its will vary d epen d in g on the output vi d eo stan d ar d sele c te d . r/w ? 24h 2-0 run_win d ow - c ontrols the output frequen c y error in the c ase of a missin g or mis-time d h referen c e transition. the d efault value of this re g ister allows the d evi c e to maintain g enlo c k throu g h one missin g input h pulse. this feature c an b e d isa b le d b y pro g rammin g run_win d ow = 000 b . in this c ase, the d evi c e will imme d iately rea c t to any d istur b an c e of the input h si g nal. the d efault value of these b its will vary d epen d in g on the output vi d eo stan d ar d sele c te d . referen c e: s e c tion 3.5.3 on pa g e 45 r/w ? r s vd 25h ? reserve d .?? vi d eo_ c ap_ g enlo c k2 6 h 15- 6 reserve d . s et these b its to zero when writin g to 2 6 h. ?? 2 6 h5-0 c ontrol si g nal to a d just loop b an d wi d th of vi d eo g enlo c k b lo c k. the value pro g ramme d in this re g ister must b e b etween 10 an d vi d eo_res_ g enlo c k - 21. the d efault value of this re g ister will vary d epen d in g on the output vi d eo stan d ar d sele c te d . referen c e: s e c tion 3. 6 .2 on pa g e 49 r/w ? table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 76 of 102 vi d eo_res_ g enlo c k 27h 15- 6 reserve d . s et these b its to zero when writin g to 27h. ?? 27h 5-0 c ontrol si g nal to a d just loop b an d wi d th of vi d eo g enlo c k b lo c k. the value pro g ramme d in this re g ister must b e b etween 32 an d 42. the d efault value of this re g ister will vary d epen d in g on the output vi d eo stan d ar d sele c te d . referen c e: s e c tion 3. 6 .2 on pa g e 49 r/w ? r s vd 28h-2bh ? reserve d ?? p c lk1_phase/divi d e2 c h 15-7 reserve d . s et these b its to zero when writin g to 2 c h. ?? 2 c h 6c urrent_p1 - sele c ts the c urrent d rive c apa b ility of the p c lk1 pin. s et this b it hi g h for hi g h c urrent d rive. otherwise, the c urrent d rive will b e low. referen c e: s e c tion 3.7.1 on pa g e 52 r/w 0 2 c h5-2p c lk1_phase - a d justs the output phase of the p c lk1 c lo c k with respe c t to the timin g output pins. phase is d elaye d in 700ps (nominal) in c rements as shown in ta b le 3- 6 . referen c e: s e c tion 3.7.1 on pa g e 52 r/w 0 2 c h1divi d e_by_4 - set this b it hi g h to d ivi d e the output p c lk1 b y four. note: s ettin g this b it an d b it 0 simultaneously hi g h will hol d the p c lk1 pin low. referen c e: s e c tion 3.7.1 on pa g e 52 r/w 0 2 c h0divi d e_by_2 - set this b it hi g h to d ivi d e the output p c lk1 b y two. note: s ettin g this b it an d b it 1 simultaneously hi g h will hol d the p c lk1 pin low. referen c e: s e c tion 3.7.1 on pa g e 52 r/w 0 table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 77 of 102 p c lk2_phase/divi d e 2dh 15-7 reserve d . s et these b its to zero when writin g to 2dh. ?? 2dh 6c urrent_p2 - sele c ts the c urrent d rive c apa b ility of the p c lk2 pin. s et this b it hi g h for hi g h c urrent d rive. otherwise, the c urrent d rive will b e low. referen c e: s e c tion 3.7.1 on pa g e 52 r/w 0 2dh 5-2 p c lk2_phase - a d justs the output phase of the p c lk2 c lo c k with respe c t to the timin g output pins. phase is d elaye d in 700ps (nominal) in c rements as shown in ta b le 3- 6 . referen c e: s e c tion 3.7.1 on pa g e 52 r/w 0 2dh 1 divi d e_by_4 - set this b it hi g h to d ivi d e the output p c lk2 b y four. note: s ettin g this b it an d b it 0 simultaneously hi g h will hol d the p c lk2 pin low. referen c e: s e c tion 3.7.1 on pa g e 52 r/w 0 2dh 0 divi d e_by_2 - set this b it hi g h to d ivi d e the output p c lk2 b y two. note: s ettin g this b it an d b it 1 simultaneously hi g h will hol d the p c lk2 pin low. referen c e: s e c tion 3.7.1 on pa g e 52 r/w 0 p c lk3_phase/divi d e 2eh 15- 6 reserve d . s et these b its to zero when writin g to 2eh. ?? 2eh 5-2 p c lk3_phase - a d justs the output phase of the p c lk3/p c lk3 c lo c k with respe c t to the timin g output pins. phase is d elaye d in 700ps (nominal) in c rements as shown in ta b le 3- 6 . referen c e: s e c tion 3.7.1 on pa g e 52 r/w 0 2eh 1 divi d e_by_4 - set this b it hi g h to d ivi d e the output p c lk3/p c lk3 b y four. s ettin g this b it an d b it 0 simultaneously hi g h will g ive the full rate vi d eo c lo c k on the p c lk3 / p c lk3 pins. referen c e: s e c tion 3.7.1 on pa g e 52 r/w 0 2eh 0 divi d e_by_2 - set this b it hi g h to d ivi d e the output p c lk3/p c lk3 b y two. s ettin g this b it an d b it 1 simultaneously hi g h will g ive the full rate vi d eo c lo c k on the p c lk3 / p c lk3 pins. referen c e: s e c tion 3.7.1 on pa g e 52 r/w 0 p c lk3_tristate 2fh 15-2 reserve d . s et these b its to zero when writin g to 2fh. ?? 2fh 1-0 s et these b its to 11 b to tristate the p c lk3 / p c lk3 pins. referen c e: s e c tion 3.7.1 on pa g e 52 r/w 00 b table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 78 of 102 r s vd 2fh - 30h ? reserve d .?? au d io_ c ontrol ( gs 4901b only) 31h 15-10 reserve d . s et these b its to zero when writin g to 31h. ?? 31h 9-7 af s _reset_win d ow - these b its may b e use d to a d just the value b y whi c h the au d io c lo c k c ounters are allowe d to d rift from the output af s pulse. the en c o d in g s c heme for this re g ister is shown in ta b le 3-9 . note: the d efault settin g of this re g ister will provi d e a reset win d ow that is suffi c ient for most stan d ar d s. to maintain c orre c t au d io c lo c k frequen c ies for some ve s a stan d ar d s, the reset win d ow may have to b e in c rease d from its d efault settin g . in this c ase, set the value of this re g ister to 1xx. s ee ta b le 3-9 . referen c e: s e c tion 3.7.2 on pa g e 54 r/w 010 b 31h 6 reserve d . s et this it to zero when writin g to 31h. r/w 0 31h 5 ena b le_384fs - set this b it hi g h to ena b le the 384fs an d 192fs au d io c lo c k outputs. this must b e set in a dd ition to re g isters 3fh to 41h. note: if this b it is hi g h, then a 512fs au d io c lo c k will have a 33% d uty c y c le when fs = 9 6 khz. referen c e: s e c tion 3.7.2 on pa g e 54 r/w 0 31h 4-3 reserve d . s et these b its to zero when writin g to 31h. ?? 31h 2 host_a s r_ s el - set this b it hi g h to sele c t the au d io sample rate usin g re g ister 32h instea d of the external a s r_ s el[2:0] pins. the external a s r_ s el[2:0] pins will b e i g nore d , b ut shoul d not b e left floatin g . referen c e: s e c tion 3.7.2 on pa g e 54 r/w 0 31h 1 af s _f_pulse - set this b it to 1 to stret c h the af s pulse d uration from 1 line to 1 fiel d . referen c e: s e c tion 3.8.2 on pa g e 59 r/w 0 31h 0 af s _reset_disa b le - set this b it hi g h to d isa b le the 10fid input referen c e pin from resettin g the output af s pulse. if this b it is set hi g h, the output af s pulse will free-run or may b e reset usin g re g ister 1ah. the external 10fid pin shoul d not b e left floatin g . referen c e: s e c tion 3.8.2 on pa g e 59 r/w 0 table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 79 of 102 a s r_ s el[2:0] ( gs 4901b only) 32h 15-3 reserve d . s et these b its to zero when writin g to 32h. ?? 32h 2-0 repla c es the external a s r_ s el[2:0] pins when host_a s r_ s ele c t ( b it 2 of a dd ress 31h) is hi g h. the d efault settin g of this re g ister c orrespon d s to an au d io sample rate of 48khz. referen c e: s e c tion 3.7.2 on pa g e 54 r/w 011 b r s vd 33h - 38h ? reserve d .?? au d io_ c ap_ g enlo c k ( gs 4901b only) 39h 15- 6 reserve d . s et these b its to zero when writin g to 39h. ?? 39h 5-0 c ontrol si g nal to a d just loop b an d wi d th of au d io g enlo c k b lo c k. the value pro g ramme d in this re g ister must b e b etween 10 an d au d io_res_ g enlo c k - 21. the d efault value of this re g ister will d epen d on the fun d amental samplin g frequen c y sele c te d . referen c e: s e c tion 3. 6 .2 on pa g e 49 r/w ? au d io_res_ g enlo c k ( gs 4901b only) 3ah 15- 6 reserve d . s et these b its to zero when writin g to 3ah. ?? 3ah 5-0 c ontrol si g nal to a d just loop b an d wi d th of au d io g enlo c k b lo c k. the value pro g ramme d in this re g ister must b e b etween 32 an d 42. the d efault value of this re g ister will d epen d on the fun d amental samplin g frequen c y sele c te d . referen c e: s e c tion 3. 6 .2 on pa g e 49 r/w ? r s vd 3bh-3eh ? reserve d ?? a c lk1_fs_multiple ( gs 4901b only) 3fh 15-3 reserve d . s et these b its to zero when writin g to 3fh. ?? 3fh 2-0 the user may set this re g ister to sele c t the d esire d frequen c y of the au d io c lo c k on a c lk1 (a multiple of the fun d amental samplin g rate, fs). the au d io c lo c k frequen c y may b e set as: 512fs, 384fs, 25 6 fs, 192fs, 128fs, 6 4fs, fs, or z- b it. s ee ta b le 3-8 for more d etails. note: to output a frequen c y of 348fs or 192fs, b it 5 of re g ister 31h must also b e set hi g h. referen c e: s e c tion 3.7.2 on pa g e 54 r/w 0 table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 80 of 102 a c lk2_fs_multiple ( gs 4901b only) 40h 15-3 reserve d . s et these b its to zero when writin g to 40h. ?? 40h 2-0 the user may set this re g ister to sele c t the d esire d frequen c y of the au d io c lo c k on a c lk2 (a multiple of the fun d amental samplin g rate, fs). the au d io c lo c k frequen c y may b e set as: 512fs, 384fs, 25 6 fs, 192fs, 128fs, 6 4fs, fs, or z- b it. s ee ta b le 3-8 for more d etails. note: to output a frequen c y of 348fs or 192fs, b it 5 of re g ister 31h must also b e set hi g h. referen c e: s e c tion 3.7.2 on pa g e 54 r/w 0 a c lk3_fs_multiple ( gs 4901b only) 41h 15-3 reserve d . s et these b its to zero when writin g to 41h. ?? 41h 2-0 the user may set this re g ister to sele c t the d esire d frequen c y of the au d io c lo c k on a c lk3 (a multiple of the fun d amental samplin g rate, fs). the au d io c lo c k frequen c y may b e set as: 512fs, 384fs, 25 6 fs, 192fs, 128fs, 6 4fs, fs, or z- b it. s ee ta b le 3-8 for more d etails. note: to output a frequen c y of 348fs or 192fs, b it 5 of re g ister 31h must also b e set hi g h. referen c e: s e c tion 3.7.2 on pa g e 54 r/w 0 r s vd 42h ? reserve d .?? output_ s ele c t_1 43h 15-5 reserve d . s et these b its to zero when writin g to 43h. ?? 43h 4 c urrent_1 - sele c ts the c urrent d rive c apa b ility of the timin g _out_1 pin. s et this b it hi g h for hi g h c urrent d rive. otherwise, the c urrent d rive will b e low. referen c e: s e c tion 3.8.4 on pa g e 6 2 r/w 0 43h 3-0 this re g ister is use d to sele c t one of the 10 pre-pro g ramme d or 4 user pro g ramme d timin g si g nals availa b le for output on the timin g _out_1 pin. s ee ta b le 3-11 for more d etails. note: the d efault settin g of this re g ister is 0001 b , whi c h c orrespon d s to h s yn c . referen c e: s e c tion 3.8.4 on pa g e 6 2 r/w 0001 b table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 81 of 102 output_ s ele c t_2 44h 15-5 reserve d . s et these b its to zero when writin g to 44h. ?? 44h 4 c urrent_2 - sele c ts the c urrent d rive c apa b ility of the timin g _out_2 pin. s et this b it hi g h for hi g h c urrent d rive. otherwise, the c urrent d rive will b e low. referen c e: s e c tion 3.8.4 on pa g e 6 2 r/w 0 44h 3-0 this re g ister is use d to sele c t one of the 10 pre-pro g ramme d or 4 user pro g ramme d timin g si g nals availa b le for output on the timin g _out_2 pin. s ee ta b le 3-11 for more d etails. note: the d efault settin g of this re g ister is 0010 b , whi c h c orrespon d s to h blankin g . referen c e: s e c tion 3.8.4 on pa g e 6 2 r/w 0010 b output_ s ele c t_3 45h 15-5 reserve d . s et these b its to zero when writin g to 45h. ?? 45h 4 c urrent_3 - sele c ts the c urrent d rive c apa b ility of the timin g _out_3 pin. s et this b it hi g h for hi g h c urrent d rive. otherwise, the c urrent d rive will b e low. referen c e: s e c tion 3.8.4 on pa g e 6 2 r/w 0 45h 3-0 this re g ister is use d to sele c t one of the 10 pre-pro g ramme d or 4 user pro g ramme d timin g si g nals availa b le for output on the timin g _out_3 pin. s ee ta b le 3-11 for more d etails. note: the d efault settin g of this re g ister is 0011 b , whi c h c orrespon d s to v s yn c . referen c e: s e c tion 3.8.4 on pa g e 6 2 r/w 0011 b output_ s ele c t_4 4 6 h 15-5 reserve d . s et these b its to zero when writin g to 4 6 h. ?? 4 6 h4 c urrent_4 - sele c ts the c urrent d rive c apa b ility of the timin g _out_4 pin. s et this b it hi g h for hi g h c urrent d rive. otherwise, the c urrent d rive will b e low. referen c e: s e c tion 3.8.4 on pa g e 6 2 r/w 0 4 6 h3-0this re g ister is use d to sele c t one of the 10 pre-pro g ramme d or 4 user pro g ramme d timin g si g nals availa b le for output on the timin g _out_4 pin. s ee ta b le 3-11 for more d etails. note: the d efault settin g of this re g ister is 0100 b , whi c h c orrespon d s to v blankin g . referen c e: s e c tion 3.8.4 on pa g e 6 2 r/w 0100 b table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 82 of 102 output_ s ele c t_5 47h 15-5 reserve d . s et these b its to zero when writin g to 47h. ?? 47h 4 c urrent_5 - sele c ts the c urrent d rive c apa b ility of the timin g _out_5 pin. s et this b it hi g h for hi g h c urrent d rive. otherwise, the c urrent d rive will b e low. referen c e: s e c tion 3.8.4 on pa g e 6 2 r/w 0 47h 3-0 this re g ister is use d to sele c t one of the 10 pre-pro g ramme d or 4 user pro g ramme d timin g si g nals availa b le for output on the timin g _out_5 pin. s ee ta b le 3-11 for more d etails. note: the d efault settin g of this re g ister is 0101 b , whi c h c orrespon d s to f s yn c . referen c e: s e c tion 3.8.4 on pa g e 6 2 r/w 0101 b output_ s ele c t_ 6 48h 15-5 reserve d . s et these b its to zero when writin g to 48h. ?? 48h 4 c urrent_ 6 - sele c ts the c urrent d rive c apa b ility of the timin g _out_ 6 pin. s et this b it hi g h for hi g h c urrent d rive. otherwise, the c urrent d rive will b e low. referen c e: s e c tion 3.8.4 on pa g e 6 2 r/w 0 48h 3-0 this re g ister is use d to sele c t one of the 10 pre-pro g ramme d or 4 user pro g ramme d timin g si g nals availa b le for output on the timin g _out_ 6 pin. s ee ta b le 3-11 for more d etails. note: the d efault settin g of this re g ister is 0110 b , whi c h c orrespon d s to f di g ital. referen c e: s e c tion 3.8.4 on pa g e 6 2 r/w 0110 b output_ s ele c t_7 49h 15-5 reserve d . s et these b its to zero when writin g to 49h. ?? 49h 4 c urrent_7 - sele c ts the c urrent d rive c apa b ility of the timin g _out_7 pin. s et this b it hi g h for hi g h c urrent d rive. otherwise, the c urrent d rive will b e low. referen c e: s e c tion 3.8.4 on pa g e 6 2 r/w 0 49h 3-0 this re g ister is use d to sele c t one of the 10 pre-pro g ramme d or 4 user pro g ramme d timin g si g nals availa b le for output on the timin g _out_7 pin. s ee ta b le 3-11 for more d etails. note: the d efault settin g of this re g ister is 0111 b , whi c h c orrespon d s to 10fid. referen c e: s e c tion 3.8.4 on pa g e 6 2 r/w 0111 b table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 83 of 102 output_ s ele c t_8 4ah 15-5 reserve d . s et these b its to zero when writin g to 4ah. ?? 4ah 4 c urrent_8 - sele c ts the c urrent d rive c apa b ility of the timin g _out_8 pin. s et this b it hi g h for hi g h c urrent d rive. otherwise, the c urrent d rive will b e low. referen c e: s e c tion 3.8.4 on pa g e 6 2 r/w 0 4ah 3-0 this re g ister is use d to sele c t one of the 10 pre-pro g ramme d or 4 user pro g ramme d timin g si g nals availa b le for output on the timin g _out_8 pin. s ee ta b le 3-11 for more d etails. note: the d efault settin g of this re g ister is 1000 b , whi c h c orrespon d s to display ena b le (de). referen c e: s e c tion 3.8.4 on pa g e 6 2 r/w 1000 b r s vd 4bh ? reserve d .?? vi d eo_ c ontrol 4 c h 15-5 reserve d . s et these b its to zero when writin g to 4 c h. ?? 4 c h 4 10fid_f_pulse - set this b it hi g h to stret c h the 10fid pulse d uration from 1 line to 1 fiel d . referen c e: s e c tion 3.8.1 on pa g e 58 r/w 0 4 c h 3-2 reserve d . s et these b its to zero when writin g to 4 c h. ?? 4 c h 1 host_vid_ s td - set this b it hi g h to sele c t the output vi d eo stan d ar d usin g re g ister 4dh instea d of the external vid_ s td[5:0] pins. the external vid_ s td[5:0] pins will b e i g nore d , b ut shoul d not b e left floatin g . referen c e: s e c tion 1.4 on pa g e 19 r/w 0 4 c h 0 reserve d . s et this b it to zero when writin g to 4 c h. ? ? vid_ s td[5:0] 4dh 15- 6 reserve d . s et these b its to zero when writin g to 4dh. ?? 4dh 5-0 repla c es the external vid_ s td[5:0] pins when vid_from_host ( b it 1 of a dd ress 4 c h) is hi g h. referen c e: s e c tion 1.4 on pa g e 19 r/w 00h r s vd 4eh-55h ? reserve d ?? polarity 5 6 h 15-10 reserve d . s et these b its to zero when writin g to 5 6 h. ?? table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 84 of 102 polarity 5 6 h9af s ( gs 4901b only)- set this b it hi g h to invert the polarity of the af s timin g output si g nal. by d efault, the af s si g nal is hi g h for the d uration of the first line of the n?th vi d eo frame to in d i c ate that the a c lk d ivi d ers have b een reset at the start of line 1 of that frame. note: the gs 4900b d oes not g enerate an af s pulse an d will i g nore the settin g of this b it. referen c e: ta b le 1-3 r/w 0 5 6 h 8 10fid - set this b it hi g h to invert the polarity of the 10fid timin g output si g nal. by d efault, the 10fid si g nal will g o hi g h for one line at the start of the 10-fiel d sequen c e. referen c e: ta b le 1-3 r/w 0 5 6 h 7 de - set this b it hi g h to invert the polarity of the de timin g output si g nal. by d efault, the de si g nal will b e hi g h whenever pixel information is to b e d isplaye d on the d isplay d evi c e referen c e: ta b le 1-3 r/w 0 5 6 h 6 reserve d . s et this b it to zero when writin g to 5 6 h. ? ? 5 6 h5f_di g ital - set this b it hi g h to invert the polarity of the f di g ital timin g output si g nal. by d efault, the f di g ital si g nal will b e hi g h for the entire perio d of fiel d 1. referen c e: ta b le 1-3 r/w 0 5 6 h4f_ s yn c - set this b it hi g h to invert the polarity of the f s yn c timin g output si g nal. by d efault, the f s yn c si g nal will b e hi g h for the entire perio d of fiel d 1. referen c e: ta b le 1-3 r/w 0 5 6 h 3 v_blankin g - set this b it hi g h to invert the polarity of the v blankin g timin g output si g nal. by d efault, the v blankin g si g nal will b e low for the portion of the fiel d /frame c ontainin g vali d vi d eo d ata. referen c e: ta b le 1-3 r/w 0 5 6 h2v_ s yn c - set this b it hi g h to invert the polarity of the v s yn c timin g output si g nal. by d efault, the v s yn c si g nal is a c tive low. referen c e: ta b le 1-3 r/w 0 table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 85 of 102 polarity 5 6 h 1 h_blankin g - set this b it hi g h to invert the polarity of the h blankin g timin g output si g nal. by d efault, the h blankin g si g nal will b e low for the portion of the vi d eo line c ontainin g vali d vi d eo samples. referen c e: ta b le 1-3 r/w 0 5 6 h0h_ s yn c - set this b it hi g h to invert the polarity of the h s yn c timin g output si g nal. by d efault, the h s yn c si g nal is a c tive low. referen c e: ta b le 1-3 r/w 0 h_ s tart_1 57h 15-0 the value pro g ramme d in this re g ister in d i c ates the pixel start point for the lea d in g e dg e of the user-pro g ramme d h s yn c si g nal u s er1_h. note: the value pro g ramme d in this re g ister must b e less than the value pro g ramme d in h_ s top_1. referen c e: s e c tion 3.8.3 on pa g e 6 0 r/w 0 h_ s top_1 58h 15-0 the value pro g ramme d in this re g ister in d i c ates the pixel en d point for the trailin g e dg e of the user-pro g ramme d h s yn c si g nal u s er1_h. note: the value pro g ramme d in this re g ister must not ex c ee d the maximum num b er of c lo c k perio d s per line of the out g oin g stan d ar d . referen c e: s e c tion 3.8.3 on pa g e 6 0 r/w 0 v_ s tart_1 59h 15 reserve d . s et this b it to zero when writin g to 59h. ? ? 59h 14-0 the value pro g ramme d in this re g ister in d i c ates the start line num b er of the lea d in g e dg e of the user-pro g ramme d v s yn c si g nal u s er1_v. for interla c e d output stan d ar d s, this value c orrespon d s to the o dd fiel d num b er. note: the value pro g ramme d in this re g ister must b e less than the value pro g ramme d in v_ s top_1. referen c e: s e c tion 3.8.3 on pa g e 6 0 r/w 0 v_ s top_1 5ah 15 reserve d . s et this b it to zero when writin g to 5ah. ? ? 5ah 14-0 the value pro g ramme d in this re g ister in d i c ates the en d line num b er of the trailin g e dg e of the user-pro g ramme d v s yn c si g nal u s er1_v. for interla c e d output stan d ar d s, this value c orrespon d s to the o dd fiel d num b er. note: the value pro g ramme d in this re g ister must not ex c ee d the maximum num b er of lines per fiel d of the out g oin g stan d ar d . referen c e: s e c tion 3.8.3 on pa g e 6 0 r/w 0 table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 86 of 102 operator_polarity_1 5bh 15-4 reserve d . s et these b its to zero when writin g to 5bh. ?? 5bh 3 polarity_1 - use this b it to invert the polarity of the final u s er1 si g nal. by d efault, the polarity of the user pro g ramme d si g nals is a c tive low. the polarity may b e swit c he d to a c tive hi g h b y settin g this b it low. referen c e: s e c tion 3.8.3 on pa g e 6 0 r/w 1 5bh 2 and_1 - lo g i c al operator: u s er1_h and u s er1_v s et this b it hi g h to output a si g nal that is only a c tive when b oth u s er1_h an d u s er1_v are a c tive. when this b it is hi g h, b it 1 an d b it 0 of this re g ister will b e i g nore d . referen c e: s e c tion 3.8.3 on pa g e 6 0 r/w 0 5bh 1 or_1 - lo g i c al operator: u s er1_h or u s er1_v s et this b it hi g h to output a si g nal that is a c tive whenever u s er1_h or u s er1_v are a c tive. when this b it is hi g h b it 0 of this re g ister will b e i g nore d . referen c e: s e c tion 3.8.3 on pa g e 6 0 r/w 0 5bh 0 xor_1 - lo g i c al operator: u s er1_h xor u s er1_v s et this b it hi g h to output a si g nal with the followin g attri b utes: s i g nal b e c omes a c tive when either u s er1_h or u s er1_v is a c tive. s i g nal is ina c tive when u s er1_h an d u s er1_v are b oth a c tive or b oth ina c tive. referen c e: s e c tion 3.8.3 on pa g e 6 0 r/w 0 h_ s tart_2 5 c h 15-0 the value pro g ramme d in this re g ister in d i c ates the pixel start point for the lea d in g e dg e of the user-pro g ramme d h s yn c si g nal u s er2_h. note: the value pro g ramme d in this re g ister must b e less than the value pro g ramme d in h_ s top_2 referen c e: s e c tion 3.8.3 on pa g e 6 0 r/w 0 h_ s top_2 5dh 15-0 the value pro g ramme d in this re g ister in d i c ates the pixel en d point for the trailin g e dg e of the user-pro g ramme d h s yn c si g nal u s er2_h. note: the value pro g ramme d in this re g ister must not ex c ee d the maximum num b er of c lo c k perio d s per line of the out g oin g stan d ar d . referen c e: s e c tion 3.8.3 on pa g e 6 0 r/w 0 table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 87 of 102 v_ s tart_2 5eh 15 reserve d . s et this b it to zero when writin g to 5eh. ? ? 5eh 14-0 the value pro g ramme d in this re g ister in d i c ates the start line num b er of the lea d in g e dg e of the user-pro g ramme d v s yn c si g nal u s er2_v. for interla c e d output stan d ar d s, this value c orrespon d s to the o dd fiel d line num b er. note: the value pro g ramme d in this re g ister must b e less than the value pro g ramme d in v_ s top_2. referen c e: s e c tion 3.8.3 on pa g e 6 0 r/w 0 v_ s top_2 5fh 15 reserve d . s et this b it to zero when writin g to 5fh. ? ? 5fh 14-0 the value pro g ramme d in this re g ister in d i c ates the en d line num b er of the trailin g e dg e of the user-pro g ramme d v s yn c si g nal u s er2_v. for interla c e d output stan d ar d s, this value c orrespon d s to the o dd fiel d line num b er. note: the value pro g ramme d in this re g ister must not ex c ee d the maximum num b er of lines per fiel d of the out g oin g stan d ar d . referen c e: s e c tion 3.8.3 on pa g e 6 0 r/w 0 operator_polarity_2 6 0h 15-4 reserve d . s et these b its to zero when writin g to 6 0h. ?? 6 0h 3 polarity_2 - use this b it to invert the polarity of the final u s er2 si g nal. by d efault, the polarity of the user pro g ramme d si g nals is a c tive low. the polarity may b e swit c he d to a c tive hi g h b y settin g this b it low. referen c e: s e c tion 3.8.3 on pa g e 6 0 r/w 1 6 0h 2 and_2 - lo g i c al operator: u s er2_h and u s er2_v s et this b it hi g h to output a si g nal that is only a c tive when b oth u s er2_h an d u s er2_v are a c tive. when this b it is hi g h, b it 1 an d b it 0 of this re g ister will b e i g nore d . referen c e: s e c tion 3.8.3 on pa g e 6 0 r/w 0 6 0h 1 or_2 - lo g i c al operator: u s er2_h or u s er2_v s et this b it hi g h to output a si g nal that is a c tive whenever u s er2_h or u s er2_v are a c tive. when this b it is hi g h b it 0 of this re g ister will b e i g nore d . referen c e: s e c tion 3.8.3 on pa g e 6 0 r/w 0 6 0h 0 xor_2 - lo g i c al operator: u s er2_h xor u s er2_v s et this b it hi g h to output a si g nal with the followin g attri b utes: s i g nal b e c omes a c tive when either u s er2_h or u s er2_v is a c tive. s i g nal is ina c tive when u s er2_h an d u s er2_v are b oth a c tive or b oth ina c tive. referen c e: s e c tion 3.8.3 on pa g e 6 0 r/w 0 table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 88 of 102 h_ s tart_3 6 1h 15-0 the value pro g ramme d in this re g ister in d i c ates the pixel start point for the lea d in g e dg e of the user-pro g ramme d h s yn c si g nal u s er3_h. note: the value pro g ramme d in this re g ister must b e less than the value pro g ramme d in h_ s top_3. referen c e: s e c tion 3.8.3 on pa g e 6 0 r/w 0 h_ s top_3 6 2h 15-0 the value pro g ramme d in this re g ister in d i c ates the pixel en d point for the trailin g e dg e of the user-pro g ramme d h s yn c si g nal u s er3_h. note: the value pro g ramme d in this re g ister must not ex c ee d the maximum num b er of c lo c k perio d s per line of the out g oin g stan d ar d . referen c e: s e c tion 3.8.3 on pa g e 6 0 r/w 0 v_ s tart_3 6 3h 15 reserve d . s et this b it to zero when writin g to 6 3h. ? ? 6 3h 14-0 the value pro g ramme d in this re g ister in d i c ates the start line num b er of the lea d in g e dg e of the user-pro g ramme d v s yn c si g nal u s er3_v. for interla c e d output stan d ar d s, this value c orrespon d s to the o dd fiel d line num b er. note: the value pro g ramme d in this re g ister must b e less than the value pro g ramme d in v_ s top_3. referen c e: s e c tion 3.8.3 on pa g e 6 0 r/w 0 v_ s top_3 6 4h 15 reserve d . s et this b it to zero when writin g to 6 4h. ? ? 6 4h 14-0 the value pro g ramme d in this re g ister in d i c ates the en d line num b er of the trailin g e dg e of the user-pro g ramme d v s yn c si g nal u s er3_v. for interla c e d output stan d ar d s, this value c orrespon d s to the o dd fiel d line num b er. note: the value pro g ramme d in this re g ister must not ex c ee d the maximum num b er of lines per fiel d of the out g oin g stan d ar d . referen c e: s e c tion 3.8.3 on pa g e 6 0 r/w 0 table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 89 of 102 operator_polarity_3 6 5h 15-4 reserve d . s et these b its to zero when writin g to 6 5h. ?? 6 5h 3 polarity_3 - use this b it to invert the polarity of the final u s er3 si g nal. by d efault, the polarity of the user pro g ramme d si g nals is a c tive low. the polarity may b e swit c he d to a c tive hi g h b y settin g this b it low. referen c e: s e c tion 3.8.3 on pa g e 6 0 r/w 1 6 5h 2 and_3 - lo g i c al operator: u s er3_h and u s er3_v s et this b it hi g h to output a si g nal that is only a c tive when b oth u s er3_h an d u s er3_v are a c tive. when this b it is hi g h, b it 1 an d b it 0 of this re g ister will b e i g nore d . referen c e: s e c tion 3.8.3 on pa g e 6 0 r/w 0 6 5h 1 or_3 - lo g i c al operator: u s er3_h or u s er3_v s et this b it hi g h to output a si g nal that is a c tive whenever u s er3_h or u s er3_v are a c tive. when this b it is hi g h b it 0 of this re g ister will b e i g nore d . referen c e: s e c tion 3.8.3 on pa g e 6 0 r/w 0 6 5h 0 xor_3 - lo g i c al operator: u s er3_h xor u s er3_v s et this b it hi g h to output a si g nal with the followin g attri b utes: s i g nal b e c omes a c tive when either u s er3_h or u s er3_v is a c tive. s i g nal is ina c tive when u s er3_h an d u s er3_v are b oth a c tive or b oth ina c tive. referen c e: s e c tion 3.8.3 on pa g e 6 0 r/w 0 h_ s tart_4 66 h 15-0 the value pro g ramme d in this re g ister in d i c ates the pixel start point for the lea d in g e dg e of the user-pro g ramme d h s yn c si g nal u s er4_h. note: the value pro g ramme d in this re g ister must b e less than the value pro g ramme d in h_ s top_4. referen c e: s e c tion 3.8.3 r/w 0 h_ s top_4 6 7h 15-0 the value pro g ramme d in this re g ister in d i c ates the pixel en d point for the trailin g e dg e of the user-pro g ramme d h s yn c si g nal u s er4_h. note: the value pro g ramme d in this re g ister must not ex c ee d the maximum num b er of c lo c k perio d s per line of the out g oin g stan d ar d . referen c e: s e c tion 3.8.3 on pa g e 6 0 r/w 0 table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 90 of 102 v_ s tart_4 6 8h 15 reserve d . s et this b it to zero when writin g to 6 8h. ? ? 6 8h 14-0 the value pro g ramme d in this re g ister in d i c ates the start line num b er of the lea d in g e dg e of the user-pro g ramme d v s yn c si g nal u s er4_v. for interla c e d output stan d ar d s, this value c orrespon d s to the o dd fiel d line num b er. note: the value pro g ramme d in this re g ister must b e less than the value pro g ramme d in v_ s top_4. referen c e: s e c tion 3.8.3 on pa g e 6 0 r/w 0 v_ s top_4 6 9h 15 reserve d . s et this b it to zero when writin g to 6 9h. ? ? 6 9h 14-0 the value pro g ramme d in this re g ister in d i c ates the en d line num b er of the trailin g e dg e of the user-pro g ramme d v s yn c si g nal u s er4_v. for interla c e d output stan d ar d s, this value c orrespon d s to the o dd fiel d line num b er. note: the value pro g ramme d in this re g ister must not ex c ee d the maximum num b er of lines per fiel d of the out g oin g stan d ar d . referen c e: s e c tion 3.8.3 on pa g e 6 0 r/w 0 operator_polarity_4 6 ah 15-4 reserve d . s et these b its to zero when writin g to 6 ah. ?? 6 ah 3 polarity_4 - use this b it to invert the polarity of the final u s er4 si g nal. by d efault, the polarity of the user pro g ramme d si g nals is a c tive low. the polarity may b e swit c he d to a c tive hi g h b y settin g this b it low. referen c e: s e c tion 3.8.3 on pa g e 6 0 r/w 1 6 ah 2 and_4 - lo g i c al operator: u s er4_h and u s er4_v s et this b it hi g h to output a si g nal that is only a c tive when b oth u s er4_h an d u s er4_v are a c tive. when this b it is hi g h, b it 1 an d b it 0 of this re g ister will b e i g nore d . referen c e: s e c tion 3.8.3 on pa g e 6 0 r/w 0 6 ah 1 or_4 - lo g i c al operator: u s er4_h or u s er4_v s et this b it hi g h to output a si g nal that is a c tive whenever u s er4_h or u s er4_v are a c tive. when this b it is hi g h b it 0 of this re g ister will b e i g nore d . referen c e: s e c tion 3.8.3 on pa g e 6 0 r/w 0 6 ah 0 xor_4 - lo g i c al operator: u s er4_h xor u s er4_v s et this b it hi g h to output a si g nal with the followin g attri b utes: s i g nal b e c omes a c tive when either u s er4_h or u s er4_v is a c tive. s i g nal is ina c tive when u s er4_h an d u s er4_v are b oth a c tive or b oth ina c tive. referen c e: s e c tion 3.8.3 on pa g e 6 0 r/w 0 table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 91 of 102 ext_au d io_mo d e 81h 15-0 s et this re g ister to 20 c 1h to ena b le the exten d e d au d io mo d e of the d evi c e. to fully ena b le this mo d e, vid_ s td[5:0] must b e set to 4 d , an d the f_lo c k_mask an d v_lo c k_mask b its [4:3] of re g ister a dd ress 1 6 h must b e set to 1. note: on c e this re g ister is pro g ramme d , it must b e up d ate d usin g b it 6 of re g ister 1 6 h. referen c e: s e c tion 3.9 on pa g e 6 3 r/w 0 hd_referen c e_ena b le 82h 15-8 reserve d . s et these b its to zero when writin g to 82h. ?? 82h 7 hd_ref_ena b le - s et this b it hi g h to allow the d evi c e to re c o g nize the hd input referen c e formats that have also b een ena b le d in the referen c e_ s tan d ar d _disa b le re g ister (a dd ress 11h-13h). when this b it is set hi g h, the gs 4901b/ gs 4900b will only assert ref_lo s t when the input si g nal is remove d . referen c e: s e c tion 3.5 on pa g e 43 . r/w 0 82h 6 -0 reserve d . s et these b its to zero when writin g to 82h. ?? ln_ c ount_reset 83h 15 to gg le this b it to reset the line- b ase d c ounters in the d evi c e. this is only require d when lo c kin g the 525-line s d output stan d ar d s to the ?f/1.001? hd input referen c e stan d ar d s, and: 1. the reference has been removed and subsequently re-applied. in this case, the user should wait until the reference has been re-detected by the device, which may take up to 4 frames. see section 3.5.3 on page 45 . or 2. the device is locked to blanking signals from a deserializer, and the sdi input to the deserializer has been switched upstream from the system. see section 3.6.3 on page 52 . r/w 0 83h 14-0 reserve d . s et these b its to zero when writin g to 83h. ?? table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 92 of 102 3.11 jtag when the jtag/host input pin of the gs4901b/GS4900B is set high, the host interface port will be configured for jtag test operation. in this mode, pins 57 through 60 become tclk, tdi, tdo, and tms. in addition, the reset pin will operate as the test reset pin. boundary scan testing using the jtag interface will be enabled in this mode. there are two methods in which jtag can be used on the gs4901b/GS4900B: 1. as a stand-alone jtag interface to be used at in-circuit ate (automatic test equipment) during pcb assembly; or 2. under control of the host for applications such as system power on self tests. when the jtag tests are applied by ate, care must be taken to di sable any other devices driving the digital i/o pins. if the tests are to be applied only at ate, this can be accomplished with high-impedance buffers used in conjunction with the jtag/host input signal. this is shown in figure 3-16 . fi g ure 3-1 6 : in- c ir c uit j ta g alternatively, if the test capabilities are to be used in the system, the host may still control the jtag/host input signal, but some means for tri-stating the host must exist in order to use the interface at ate. this is represented in figure 3-17 . application host gs4911b/gs4910b cs_tms sclk_tclk sdin_tdi sdout_tdo jtag/host in-circuit ate probe
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 93 of 102 fi g ure 3-17: s ystem j ta g 3.12 device power-up 3.12.1 power supply sequencing the gs4901b/GS4900B has a recommended power supply sequence. to ensure correct power-up, the analog_vdd and core_vdd power pins should be powered before io_vdd. device pins may be driven prior to power-up without causing damage. 3.13 device reset in order to initialize operating conditions to their default states, the application layer must hold the reset signal low during power up and for a minimum of 500us after the last supply has reached its operating voltage. application host gs4911b/gs4910b cs_tms sclk_tclk sdin_tdi sdout_tdo jtag/host in-circuit ate probe tri-state
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 94 of 102 4. application reference design 4.1 gs4901b typical application circuit note: for a solution with the lowest output jitter, the gs9062 or gs9092a serializers are recommended for use with the gs4901b/GS4900B. controlled impedance 100-ohms differential note: the gs4911a inputs are 5v tolerant for 3v3 i/o operation only (io_vdd=3v3) the 10fid input must be grounded if it will not be used vid_pll_gnd 4 vid_pll_vdd 3 xtal_vdd 5 x1 6 x2 7 xtal_gnd 8 core_gnd 9 phs_gnd 55 phs_vdd 54 analog_vdd 10 nc 11 analog_gnd 12 aud_pll_gnd 13 aud_pll_vdd 14 10fid 15 hsync 16 vsync 17 io_vdd 18 fsync 19 nc 20 vid_std0 21 vid_std1 22 vid_std2 23 vid_std3 24 vid_std4 25 vid_std5 27 aclk1 28 aclk2 29 aclk3 30 io_vdd 31 core_vdd 26 asr_sel2 32 asr_sel1 33 asr_sel0 34 timing_out1 35 timing_out2 36 io_vdd 38 timing_out4 39 timing_out3 37 timing_out5 40 lvds/pclk3_vdd 45 pclk3 46 lvds/pclk3_gnd 48 pclk3 47 pclk2 49 pclk1&2_gnd 52 pclk1 51 io_vdd 50 timing_out6 41 timing_out7 42 timing_out8 43 pclk1&2_vdd 53 lock_lost 1 ref_lost 2 genlock 64 core_vdd 44 jtag/host 56 sclk_tclk 57 sdin_tdi 58 sdout_tdo 59 cs_tms 60 reset 61 io_vdd 62 nc 63 gnd_pad 65 22r 10n 10n 10n 10n 22r 22r 22r 22r 10n 0r 22r 10n 22r 24pf 10n 22r 22r gs4901b 10n 38pf 10n 22r 22r 10n 10n 1m 22r 10n 10n 22r 1v8_pclk vdd_io 1v8_core gnd_xtal 1v8_core vdd_io vdd_io 1v8_vpll 1v8_vpll gnd_vpll 1v8_pclk vdd_io gnd_vpll 1v8_apll gnd_apll vdd_xtal gnd_xtal hsync vsync fsync 10fid aclk3 aclk2 aclk1 timing1 timing2 timing3 timing4 timing5 timing6 timing7 timing8 csb resetb sdin sdout sclk pclk2 pclk3 pclk3b pclk1 genlockb jtag/hostb vid_std0 vid_std1 vid_std2 vid_std3 asr_sel0 asr_sel2 asr_sel1 lock_lost ref_lost 27mhz
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 95 of 102 4.2 GS4900B typical application circuit note: for a solution with the lowest output jitter, the gs9062 or gs9092a serializers are recommended for use with the gs4901b/GS4900B. controlled impedance 100-ohms differential note: the gs4910a inputs are 5v tolerant for 3v3 i/o operation only (io_vdd=3v3) the 10fid input must be grounded if it will not be used vid_pll_gnd 4 vid_pll_vdd 3 xtal_vdd 5 x1 6 x2 7 xtal_gnd 8 core_gnd 9 phs_gnd 55 phs_vdd 54 analog_vdd 10 nc 11 analog_gnd 12 analog_gnd 13 analog_gnd 14 10fid 15 hsync 16 vsync 17 io_vdd 18 fsync 19 nc 20 vid_std0 21 vid_std1 22 vid_std2 23 vid_std3 24 vid_std4 25 vid_std5 27 nc 28 nc 29 nc 30 io_vdd 31 core_vdd 26 analog_gnd 32 analog_gnd 33 analog_gnd 34 timing_out1 35 timing_out2 36 io_vdd 38 timing_out4 39 timing_out3 37 timing_out5 40 lvds/pclk3_vdd 45 pclk3 46 lvds/pclk3_gnd 48 pclk3 47 pclk2 49 pclk1&2_gnd 52 pclk1 51 io_vdd 50 timing_out6 41 timing_out7 42 timing_out8 43 pclk1&2_vdd 53 lock_lost 1 ref_lost 2 genlock 64 core_vdd 44 jtag/host 56 sclk_tclk 57 sdin_tdi 58 sdout_tdo 59 cs_tms 60 reset 61 io_vdd 62 nc 63 gnd_pad 65 10n 10n 10n 10n 22r 22r 22r 10n 0r 10n 24pf 22r 10n 22r 22r GS4900B 10n 38pf 10n 22r 10n 22r 1m 10n 22r 10n 10n 22r 1v8_pclk vdd_io 1v8_core gnd_xtal 1v8_core vdd_io vdd_io 1v8_vpll 1v8_vpll gnd_vpll 1v8_pclk vdd_io gnd_vpll gnd_a vdd_xtal gnd_xtal 1v8_a gnd_a gnd_a hsync vsync fsync 10fid timing1 timing2 timing3 timing4 timing5 timing6 timing7 timing8 csb resetb sdin sdout sclk pclk2 pclk3 pclk3b pclk1 genlockb jtag/hostb vid_std0 vid_std1 vid_std2 vid_std3 lock_lost ref_lost 27mhz
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 96 of 102 5. references & relevant standards table 5-1: references & relevant standards ae s 11-1997 s yn c hronization of di g ital au d io equipment in s tu d io operations s mpte 125m-1995 c omponent vi d eo s i g nal 4:2:2 ? bit-parallel di g ital interfa c e s mpte 170m-1999 c omposite analo g vi d eo s i g nal ? nt sc for s tu d io appli c ations s mpte 244m-1995 s ystem m/nt sc c omposite vi d eo s i g nals ? bit-parallel di g ital interfa c e s mpte 2 6 0m-1999 1125/ 6 0 hi g h-definition pro d u c tion s ystem ? di g ital representation an d bit-parallel interfa c e s mpte 2 6 7m-1995 bit-parallel di g ital interfa c e ? c omponent vi d eo s i g nal 4:2:2 1 6 x9 aspe c t ratio s mpte 274m-1998 1920 x 1080 sc annin g an d analo g an d parallel di g ital interfa c es for multiple pi c ture rates s mpte 293m-199 6 720 x 483 a c tive line at 59.94-hz pro g ressive sc an pro d u c tion ? di g ital representation s mpte 29 6 m-1997 1280 x 720 sc annin g , analo g an d di g ital representation an analo g interfa c e s mpte 318m-1999 s yn c hronization of 59.94- or 50-hz relate d vi d eo an d au d io s ystems in analo g an d di g ital areas ? referen c e s i g nals s mpte 347m-2001 540 m b /s s erial di g ital interfa c e ? s our c e ima g e format mappin g s mpte rp 1 6 4-199 6 lo c ation of verti c al interval time c o d e s mpte rp 1 6 8-1993 definition of verti c al interval s wit c hin g point for s yn c hronous vi d eo s wit c hin g s mpte rp 211-2000 implementation of 24p, 25p an d 30p s e g mente d frames for 1920 x 1080 pro d u c tion format itu-r bt. 6 01-5 s tu d io en c o d in g parameters of di g ital television for s tan d ar d 4:3 an d wi d e-s c reen 1 6 :9 aspe c t ratios itu-r bt.709-4 parameter values for the hdtv s tan d ar d s for pro d u c tion an d international pro g ram ex c han g e itu-r bt.799.3 interfa c e for di g ital c omponent vi d eo s i g nals in 525-line an d 6 25-line television s ystems operatin g at the 4:4:4 level of re c ommen d ation itu-r bt. 6 01 (part a) itu-r bt.1358 s tu d io parameters of 6 25 an d 525 line pro g ressive sc an television s ystems ve s a monitor timin g s pe c ifi c ations ve s a an d in d ustry s tan d ar d s an d g ui d elines for c omputer display monitor timin g ? version 1.0, revision 0.8 (a d option date: s eptem b er 17, 1998)
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 97 of 102 6. package & ordering information 6.1 package dimensions a b 9.00 4.50 4.50 9.00 2x 2x 0.15 c 0.15 c 0.10 c 0.08 c 64x seating plane 0.90 +/- 0.10 +0.03 0.02-0.02 0.20 ref c 7.10+/-0.15 3.55 0.40+/-0.05 7.10+/-0.15 3.55 0.25+/-0.05 64x 0.10 c ab c 0.05 0.50 all dimensions in mm pin 1 area centre tab 45 45
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 98 of 102 6.2 recommended pcb footprint the center pad of the pcb footprint should be connected to the ground plane by a minimum of 36 vias. note: suggested dimensions only. final dimensio ns should conform to customer design rules and process optimizations. 6.3 packaging data note: all dimensions are in millimeters. 7.10 7.10 8.70 8.70 0.50 0.25 0.55 center pad parameter value pa c ka g e type 9mm x 9mm 6 4-pin qfn moisture s ensitivity level 3 j un c tion to c ase thermal resistan c e, j- c 9.3 c /w j un c tion to air thermal resistan c e, j-a (at zero airflow) 24. 6 c /w psi, 0.2 c /w p b -free an d roh s c ompliant yes
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 99 of 102 6.4 ordering information part video clocks audio clocks max pclk rate gs 4901b ? 54mhz gs 4900b ? 54mhz part number package temperature range gs 4901b c ne3 p b -free 6 4-pin qfn 0 c to 70 c gs 4900b c ne3 p b -free 6 4-pin qfn 0 c to 70 c
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 100 of 102 7. revision history version ecr pcn date changes and/or modifications a 138810 ? j anuary 200 6 new d o c ument. 0 140153 ? april 200 6c onvertin g to preliminary data s heet. c orre c te d loop b an d wi d th c al c ulations. up d ate d d es c ription of lo c kin g to hd formats. up d ate d power c onsumption. 1 140830 4023 6j uly 200 6c onvertin g to data s heet. mo d ifie d maximum system power values; a dd e d maximum supply c urrent information in d c ele c tri c al c hara c teristi c s . 2 141424 40495 au g ust 200 6 up d ate d terminal wi d th to 0.25+/-0.05 on pa c ka g e dimensions an d pin 1 id c han g e to 45 c hamfer. 3 1483 66 ?novem b er 2007 c orre c te d h_offset value in s e c tion 3.2.1.13.2.1.1 g enlo c k timin g offset . up d ate d power values in ta b le 2-1: d c ele c tri c al c hara c teristi c s . 4 15327 6 ?de c em b er 2009 up d ate d d o c ument with new format.
gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 101 of 102
ottawa 232 herz b er g roa d , s uite 101 kanata, ontario k2k 2a1 c ana d a phone: +1 ( 6 13) 270-0458 fax: +1 ( 6 13) 270-0429 calgary 3553 - 31st s t. n.w., s uite 210 c al g ary, al b erta t2l 2k7 c ana d a phone: +1 (403) 284-2 6 72 united kingdom north buil d in g , wal d en c ourt parsona g e lane, bishop?s s tortfor d hertfor d shire, c m23 5db unite d kin gd om phone: +44 1279 714170 fax: +44 1279 714171 india #208(a), nirmala plaza, airport roa d , forest park s quare bhu b aneswar 751009 in d ia phone: +91 ( 6 74) 6 53-4815 fax: +91 ( 6 74) 259-5733 snowbush ip - a division of gennum 439 university ave. s uite 1700 toronto, ontario m5 g 1y8 c ana d a phone: +1 (41 6 ) 925-5 6 43 fax: +1 (41 6 ) 925-0581 e-mail: sales@snow b ush. c om we b s ite: http://www.snow b ush. c om mexico 288-a paseo d e maravillas j esus ma., a g uas c alientes mexi c o 20900 phone: +1 (41 6 ) 848-0328 japan kk s hinjuku g reen tower buil d in g 27f 6 -14-1, nishi s hinjuku s hinjuku-ku, tokyo, 1 6 0-0023 j apan phone: +81 (03) 3349-5501 fax: +81 (03) 3349-5505 e-mail: g ennum-japan@ g ennum. c om we b s ite: http://www. g ennum. c o.jp ta i w a n 6 f-4, no.51, s e c .2, keelun g r d . s inyi distri c t, taipei c ity 11502 taiwan r.o. c . phone: (88 6 ) 2-8732-8879 fax: (88 6 ) 2-8732-8870 e-mail: g ennum-taiwan@ g ennum. c om germany hain b u c henstra?e 2 80935 muen c hen (muni c h), g ermany phone: +49-89-35831 6 9 6 fax: +49-89-35804 6 53 e-mail: g ennum- g ermany@ g ennum. c om north america western region 6 91 s outh milpitas blv d ., s uite #200 milpitas, c a 95035 unite d s tates phone: +1 (408) 934-1301 fax: +1 (408) 934-1029 e-mail: naw_sales@ g ennum. c om north america eastern region 4281 harvester roa d burlin g ton, ontario l7l 5m4 c ana d a phone: +1 (905) 6 32-299 6 fax: +1 (905) 6 32-2055 e-mail: nae_sales@ g ennum. c om korea 8f j innex lakeview bl dg . 6 5-2, ban g i d on g , s on g pa g u s eoul, korea 138-828 phone: +82-2-414-2991 fax: +82-2-414-2998 e-mail: g ennum-korea@ g ennum. c om document identification data sheet the product is in production. gennum reserves the right to make changes to the product at any time without notice to improve reliability, function or design, in order to provide the best product possible. gs4901b/GS4900B sd clock and timing generator with genlock data sheet 37703 - 4 december 2009 102 of 102 102 g ennum c orporation assumes no lia b ility for any errors or omissions in this d o c ument, or for the use of the c ir c uits or d evi c es d es c ri b e d herein. the sale of the c ir c uit or d evi c e d es c ri b e d herein d oes not imply any patent li c ense, an d g ennum makes no representation that the c ir c uit or d evi c e is free from patent infrin g ement. all other tra d emarks mentione d are the properties of their respe c tive owners. g ennum an d the g ennum lo g o are re g istere d tra d emarks of g ennum c orporation. ? c opyri g ht 200 6 g ennum c orporation. all ri g hts reserve d . www. g ennum. c om gennum corporate headquarters 4281 harvester roa d , burlin g ton, ontario l7l 5m4 c ana d a phone: +1 (905) 6 32-299 6 fax: +1 (905) 6 32-2055 e-mail: c orporate@ g ennum. c om www. g ennum. c om caution ele c tro s tati c s en s itive devi c e s do not open pa c ka g e s or handle ex c ept at a s tati c -free work s tation

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